A modifiedeuclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties...
详细信息
A modifiedeuclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties, an area-efficient very large scale integration (VLSI) architecture with dynamic storage technique is proposed to perform the ME algorithm. The dynamic storage technique is used to avoid data exchange and save hardware resources. The proposed architecture with dynamic storage technique can reduce 50% computation hardware area and about 30% memory hardware area. VLSI implementation results of different RS codes show that the proposed architecture is significantly area-efficient, especially for RS codes with long code lengths.
A low-complexity Reed-Solomon (RS) decoder design based on the modifiedeuclidean (ME) algorithm proposed by Truong is presented in this paper. Low complexity is achieved by reformulating Truong's ME algorithm usi...
详细信息
A low-complexity Reed-Solomon (RS) decoder design based on the modifiedeuclidean (ME) algorithm proposed by Truong is presented in this paper. Low complexity is achieved by reformulating Truong's ME algorithm using the proposed polynomial manipulation scheme so that a more compact polynomial representation can be derived. Together with the developed folding scheme and simplified boundary cell, the resulting design effectively reduces the hardware complexity while meeting the throughput requirements of optical communication systems. Experimental results demonstrate that the developed RS(255, 239) decoder, implemented in the TSMC 0.18 mu m process, can operate at up to 425 MHz and achieve a throughput rate of 3.4 Gbps with a total gate count of 11,759. Compared to related works, the proposed decoder has the lowest area requirement and the smallest area-time complexity.
This paper presents an extremely compact, highly efficient hardware implementation of the Reed Solomon (RS) decoder. Such efficiency is of critical importance for the next generation of passive optical networks featur...
详细信息
ISBN:
(纸本)9781424492688
This paper presents an extremely compact, highly efficient hardware implementation of the Reed Solomon (RS) decoder. Such efficiency is of critical importance for the next generation of passive optical networks featuring bit rates of 10 Gb/s, high bit error rates and high cost sensitivity. RS codes are widely used for error correction in optical communication networks. The central element of a t-error correcting RS decoder is the key equation solver, which is the most time-critical stage in the RS decoder operation. It uses 2t equations to determine up to 2t unknown values. A key equation solver typically performs the Berlekamp-Massey (BM) algorithm or the modifiedeuclidean (ME) algorithm. Hardware implementations of these algorithms usually include a large number of Galois Field (GF) multipliers needed to achieve the required throughput. This paper presents a scalable BM architecture and a scalable ME architecture that minimizes the number of GF multipliers by their higher utilization. This is achieved through efficient control that avoids idle cycles and also through optimal grouping of multipliers into parallel structures given the bit error distribution for the respective optical network. The major building block of this architecture is a compact, programmable GF processor (GFP) capable of high frequency operation.
This paper presents the VLSI design of a multi-mode Reed-Solomon codec. Our decoder design is based on the modifiedeuclidean (ME) algorithm and shares hardware between the ME algorithm and the computation part of the...
详细信息
ISBN:
(纸本)9781424436927
This paper presents the VLSI design of a multi-mode Reed-Solomon codec. Our decoder design is based on the modifiedeuclidean (ME) algorithm and shares hardware between the ME algorithm and the computation part of the Chien search. With its ability, to support a variety of RS(n, k, t) code parameters (0 <= n <= 255), (0 <= t <= 8) as well as different finite fields GF(2(m)), (3 <= m <= 8), this RS codec design is suitable for use in a reconfigurable baseband processing platform. Synthesis results indicate that this codec operates at a maximum frequency of 177 MHz and has a peak data processing rate of 1416 Mbps.
In current high-speed communication and storage systems, the increasing demand for providing flexible Reed-Solomon (RS) decoding solutions to multi-mode applications has created the desire of universal RS decoders. In...
详细信息
ISBN:
(纸本)9781424443345
In current high-speed communication and storage systems, the increasing demand for providing flexible Reed-Solomon (RS) decoding solutions to multi-mode applications has created the desire of universal RS decoders. In this paper, we present a high-speed area-efficient versatile RS decoder architecture based on recursive degree computationless modifiedeuclidean (rDCME) algorithm. Targeting at different practical applications, the proposed architecture is developed into two universal RS decoder designs. Arithmetic modification to Montgomery multiplication is exploited for the reduction of area. Compared with existing works, the proposed configurable designs can deliver higher data rate with relatively lower hardware complexity, thus they are good candidates for high-speed multi-mode applications.
This paper presents a low-complexity parallel Reed-Solomon (RS) (255,239) decoder architecture using a novel pipelined variable stages recursive modifiedeuclidean (ME) algorithm for optical communication. The pipelin...
详细信息
ISBN:
(纸本)0819464481
This paper presents a low-complexity parallel Reed-Solomon (RS) (255,239) decoder architecture using a novel pipelined variable stages recursive modifiedeuclidean (ME) algorithm for optical communication. The pipelined four-parallel syndrome generator is proposed. The time multiplexing and resource sharing schemes are used in the novel recursive ME algorithm to reduce the logic gate count. The new key equation solver can be shared by two decoder macro. A new Chien search cell which doesn't need initialization is proposed in the paper. The proposed decoder can be used for 2.5Gb/s data rates device. The decoder is implemented in Altera' Stratixll device. The resource utilization is reduced about 40% comparing to the conventional method.
作者：
Lee, HInha Univ
Sch Informat & Commun Engn Inchon 402751 South Korea
This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modifiedeuclidean (PrME) algorithm block for very high-speed optical communications. The RS dec...
详细信息
This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modifiedeuclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-mu m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.
This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified euclidean algorithm. A new multiplier and inversion for GF(2(m)) are implement...
详细信息
ISBN:
(纸本)5742202601
This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified euclidean algorithm. A new multiplier and inversion for GF(2(m)) are implemented on the composite field GF(2(n)) (m =2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding Latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25mum CMOS process.
A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented in this paper. It has very widely applications in DVB, HDTV and satellite commu...
详细信息
ISBN:
(纸本)0780379845
A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented in this paper. It has very widely applications in DVB, HDTV and satellite communication systems. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. The algorithms of Viterbi decoder and RS decoder are modified T-algorithrn and modified euclidean algorithm, respectively. Furthermore, The finite field multipliers and inversion over composite fields was adapted to optimize area and power in RS decoder, which reduced the area near to 25% compared to the conventional finite fields. The proposed concatenated decoder has about 81,000 gates except RAM model, which implemented in 100MHz using 0.25um CMOS process.
暂无评论