This paper presents the use of a modular, sample invariant, six samples per cycle, discrete-timemodel of a thyristor controlled series capacitor (TCSC) for output feedback-based subsynchronous resonance (SSR) damping...
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This paper presents the use of a modular, sample invariant, six samples per cycle, discrete-timemodel of a thyristor controlled series capacitor (TCSC) for output feedback-based subsynchronous resonance (SSR) damping controller (SSDC) design. An SSDC is used to alleviate the instability of torsional modes caused by external fixed capacitors used in conjunction with a TCSC. It is found that damping torque analysis-based design of an SSDC using a non-local signal like generator slip is straightforward and the resulting SSDC has a simple compensator structure. On the other hand, the residues and pole-zero configuration with the line current magnitude as a feedback signal are such that it is relatively more difficult to obtain a robust design, especially if several subsynchronous torsional modes are present. Eigenvalue analysis and digital simulation studies indicate that the TCSC model can accurately predict the behaviour of a TCSC with and without a damping controller.
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