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motion estimation algorithm with low complexity for video compression

ELECTRONICS LETTERS 2000年第18期36卷 1533-1535页

作者： Kang, HS Hyundai Elect Co Ltd Adv Tech Lab Mobile Telecom Terminal R&D CtrSeocho Ku Seoul 137070 South Korea

The author presents a new motion estimation method which reduces the computational complexity in video compression. This is achieved by skipping the motion estimation operation for macro-blocks, where it is determined... 详细信息

关键词： motion estimation Image and video coding data compression computational complexity reduction Computational complexity low complexity algorithm Video signal processing video compression video coding computational complexity motion estimation algorithm

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motion estimation algorithm USING INTERBLOCK CORRELATION

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ELECTRONICS LETTERS 1990年第5期26卷 276-277页

作者： HSIEH, CH LU, PC SHYN, JS LU, EH Department of Electrical Engineering Chung Cheng Institute of Technology Ta-Hsi Tao-Yuan WTaiwan Republic of China

A new motion estimation algorithm that exploits the motion correlation of neighbour blocks in temporal and spatial directions is presented. Preliminary results indicate that this algorithm achieves significant savings... 详细信息

关键词： image processing motion vector side information motion correlation algorithms temporal directions interblock correlation Image processing spatial directions picture processing neighbor blocks motion estimation algorithm computation time correlation methods

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motion estimation algorithm for real-time systems

Motion estimation algorithm for real-time systems

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IEEE Workshop on Signal Processing Systems Design and Implementation

作者： Shaaban, M Goel, S Bayoumi, M Univ Louisiana CACS Lafayette LA USA

ISBN: (纸本)0780385047

This paper presents an algorithmic enhancement of the full-search block-matching algorithm for motion estimation for real-time systems. The multi-stage interval based motion estimation (MIME) algorithm reduces the computational load by successively eliminating candidate blocks from the search window. The elimination process uses low bit-resolution and it is applied in multiple stages for motion vector computation. On an average, MIME eliminates more than 88% of the candidate blocks in the search window after first and second stage. Based on these results, in real-time environment, the algorithm can be stopped at any stage without incurring significant loss in motion estimation accuracy. Simulation results show that, in worst case scenario when the algorithm stops after first stage, there is an average loss of only 3dB in PSNR as compared to full-search block-matching algorithm and an average loss of 1.2dB if the algorithm is stopped after the second step.

关键词： motion estimation real-time systems video coding image resolution motion estimation algorithm full-search block-matching algorithm multi-stage interval based motion estimation algorithm computational load low bit-resolution motion vector computation real-time video systems real-time systems motion estimation Video coding image resolution

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A fast rate-optimized motion estimation algorithm for low-bit-rate video coding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1999年第7期9卷 994-1002页

作者： Ju, JCH Chen, YK Kung, SY Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

motion estimation is known to be the main bottle-neck in real-time encoding applications, and the search for an effective motion estimation algorithm (in terms of computational complexity and compression efficiency) has been a challenging problem for years. This paper describes a new block-matching algorithm that is much faster than the full search algorithm and occasionally even produces better rate-distortion curves than the full search algorithms. We observe that a piecewise continuous motion field reduces the bit rate for differentially encoded motion vectors. Our motion estimation algorithm exploits the spatial correlations of motion vectors effectively in the sense of producing better rate-distortion curves. Furthermore, we incorporate such correlations in a multiresolution framework to reduce the computational complexity, Simulation shows that this method is successful because of the homogeneous and reliable estimation of the displacement vectors, In nine out of our ten benchmark simulations, the performance of the full search algorithm and that of our subblock multiresolution method is about the same. In one out of our ten benchmark simulations, our method has improvement.

关键词： motion estimation algorithm multiresolution refinement neighborhood relaxation

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ES&IS: Enhanced Spread and Iterative Search Hardware-Friendly motion estimation algorithm for the HEVC Standard

ES&IS: Enhanced Spread and Iterative Search Hardware-Friendl...

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2013 IEEE International Conference on Electronics, Circuits, and Systems

作者： Sanchez, Gustavo Zatt, Bruno Porto, Marcelo Agostini, Luciano Fed Univ Pelotas UFPel Grp Architectures & Integrated Circuits GACI Pelotas Brazil

ISBN: (纸本)9781479924523

In this work the hardware-friendly Enhanced Spread and Iterative Search (ES&IS) motion estimation (ME) algorithm is presented and evaluated for the High Efficiency Video Coding Standard (HEVC). The ES&IS is divided in two steps: a central evaluation and a spread evaluation with a refinement. The ES&IS was compared with Enhanced Predictive Zonal Search (EPZS) using the HEVC reference software. Software evaluations showed that, in average, the ES&IS presents a 1.07% increase in bitrate and 0.05% decrease in PSNR when compared to EPZS. However, the main advantage of the ES&IS is its hardware-friendly aspect.

关键词： motion estimation algorithm HEVC Video Coding Block Matching algorithm

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A HARDWARE FRIEDLY motion estimation algorithm FOR THE EMERGENT HEVC STANDARD AND ITS LOW POWER HARDWARE DESIGN

A HARDWARE FRIEDLY MOTION ESTIMATION ALGORITHM FOR THE EMERG...

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20th IEEE International Conference on Image Processing (ICIP)

作者： Sanchez, Gustavo Porto, Marcelo Agostini, Luciano Univ Fed Pelotas Pelotas Brazil

ISBN: (纸本)9781479923410

In this paper the hardware friendly Multi Point Diamond Search (MPDS) motion estimation (ME) algorithm is evaluated in the High Efficiency Video Coding Standard (HEVC). The MPDS algorithm was implemented in HEVC reference software and its efficiency is compared with the standard HEVC fast algorithm, the Enhanced Predictive Zonal Search (EPZS). The evaluation result, in average, shows loses of only 1.7% in the compression rate and 0.05% in PSNR. However, the main advantage of the MPDS algorithm is its hardware friendly aspect and this paper also presents its hardware design focused on real time processing HD 1080p videos. The designed architecture is capable to process HD 1080p videos in real time when synthesized for TSCM 90nm technology. The MPDS algorithm has obtained a good tradeoff among quality, compression rate and costs for its hardware implementation.

关键词： motion estimation algorithm HEVC Video Coding Hardware Design

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Computation-Efficient FPGA Implementation for Flexible Triangle Search Block-Based motion estimation algorithm

Computation-Efficient FPGA Implementation for Flexible Trian...

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23rd Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Rehan, M. El-Ashry, R. El-Kamchouchi, Hassan British Univ Egypt Dept Elect & Commun Engn El Sherouk Egypt

ISBN: (纸本)9781424453771

In this paper, a computation-efficient implementation of the flexible triangle (FTS) search algorithm is presented. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work. The FTS is used for block-based motion estimation where it can locate the best matching blocks between two frames using a search triangle of flexible size and orientation. This flexibility provide the triangle with the high efficiency to locate the best matching block in fewer number of search iterations. Further analyses of the FTS performance indicates that more computation efficiency can be achieved in loading the search area and the computing the matching criterion between two macroblocks. Adjacent search areas are overlapped and consequently, the loading mechanism can be modified to load only the non-overlapped sections In addition, loading of search area and other data can start earlier parallel with the algorithm initialization. Finally, the computed SAD results can be stored and then later used instead of re-computing them again. The proposed implementation in this paper reduces the average number of cycles required to finish one macroblock search by around 26% and thus enable the video encoder to support higher frequencies or larger resolutions. The proposed technique was implemented in FPGA as part of the flexible triangle search (FTS) motion estimation algorithm.. The proposed design was implemented, simulated, and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the FTS algorithm published in previous work.

关键词： FPGA implementation block matching algorithm field programmable gate arrays flexible triangle search block image matching iterative methods motion estimation motion estimation algorithm video encoder

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A HARDWARE FRIEDLY motion estimation algorithm FOR THE EMERGENT HEVC STANDARD AND ITS LOW POWER HARDWARE DESIGN

A HARDWARE FRIEDLY MOTION ESTIMATION ALGORITHM FOR THE EMERG...

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IEEE International Conference on Image Processing

作者： Gustavo Sanchez Marcelo Porto Luciano Agostini Federal University of Pelotas Pelotas Brazil

ISBN: (纸本)9781479923427

关键词： motion estimation algorithm HEVC Video Coding Hardware Design

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Power and performance analysis of motion estimation based on hardware and software realizations

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IEEE TRANSACTIONS ON COMPUTERS 2005年第6期54卷 714-726页

作者： Yang, SQ Wolf, W Vijaykrishnan, N Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Penn State Univ Dept Comp Sci & Engn Microsyst Design Lab University Pk PA 16802 USA

motion estimation is the most computationally expensive task in MPEG-style video compression. Video compression is starting to be widely used in battery-powered terminals, but surprisingly little is known about the power consumption of modern motion estimation algorithms. This paper describes our effort to analyze the power and performance of realistic motion estimation algorithms in both hardware and software realizations. For custom hardware realizations, this paper presents a general model of VLSI motion estimation architectures. This model allows us to analyze in detail the power consumption of a large class of modern motion estimation engines that can execute the motion estimation algorithms of interest to us. We compare these algorithms in terms of their power consumption and performance. For software realizations, this paper provides the first detailed instruction-level simulation results on motion estimation based on a programmable CPU core. We analyzed various aspects of the selected motion estimation algorithms, such as search speed and power distribution. This paper provides a guideline to two types of machine designs for motion estimation: custom ASIC ( Application Specific Integrated Circuit) design and custom ASIP ( Application Specific Instruction-set Processor) designs.

关键词： motion estimation algorithm power modeling performance optimization

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Rate-optimised motion estimation

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ELECTRONICS LETTERS 2000年第14期36卷 1196-1197页

作者： Choi, SY Chae, SI Shim, YS Commun Technol Ctr Inst Adv Engn Yongin 449860 Kyonggi Do South Korea Seoul Natl Univ Dept Elect Engn Seoul 151742 South Korea

The authors propose a motion estimation (ME) algorithm fcr determining a motion vector which minimises the estimated total number of bits allocated to the motion vector and to the residual discrete cosine transform coefficients. This rate-optimised ME algorithm contributes to an improved reconstructed image quality and a reduced number of coding bits per frame.

关键词： motion vector Signal processing theory residual discrete cosine transform coefficients image quality motion estimation algorithm Codes estimated total number optimisation image coding reduced number rate-optimised motion estimation Computer vision and image processing techniques Image processing and restoration motion estimation Image and video coding Optimisation techniques vector quantisation rate-optimised ME algorithm discrete cosine transforms image sequences coding bits

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