检索结果-内蒙古大学图书馆

IEEE Asia Pacific Conference on Circuit and System (APCCAS)

作者： Leow, Yoon Hwee Siek, Liter Nanyang Technol Univ VIRTUS IC Design Ctr Excellence Singapore 639798 Singapore

ISBN: (纸本)9781424474561

multi-bit feedback has been conventionally adopted for the implementation of high performance Continuous Time Sigma Delta modulators (CTSDMs) for relaxing multiple design requirements for the system. The need for speed has rendered a large portion of the power budget to be assigned to the quantizer comparators, which often is implemented with the flash architecture. Previous researches [1-3] had proposed the concept of a tracking quantizer to reduce the number of comparators but are primarily more suited for low speed applications. In this paper, a novel technique to implement the tracking capability for high speed is presented. The simplicity of the proposed circuit results in good speed performance with power reduction to the overall multi-bit quantizer design.

关键词： multi-bit quantizer Continuous-Time (CT) sigma-delta (Sigma Delta) modulation

来源：评论

学校读者我要写书评

暂无评论

A High Speed Tracking quantizer for Continuous-Time multi-bit Sigma Delta Modulators

A High Speed Tracking Quantizer for Continuous-Time Multi-Bi...

引用

IEEE Asia Pacific Conference on Circuits and Systems

作者： Yoon Hwee Leow Liter Siek VIRTUS-IC Design Centre of Excellence Nanyang Technological University

ISBN: (纸本)9781424474547

关键词： multi-bit quantizer Continuous-Time (CT) Sigma-delta (∑Δ) modulation

来源：评论

学校读者我要写书评

暂无评论

A Partially Feedback NSSAR Embedded Third-Order Delta-Sigma Modulator With Gain-Boosted Two-Stage FIAs

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2024年第9期59卷 2735-2746页

作者： Meng, Lingxin Chen, Junsheng Zhao, Menglian Tan, Zhichao Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310063 Peoples R China Senlogics Wuxi 214063 Peoples R China

This article presents a switched-capacitor (SC) delta-sigma modulator (DSM) for low-power and high-precision applications. With a 5-bit noise-shaping (NS) successive-approximation-register (NSSAR) quantizer embedded in the 2nd-order loop filter, the system achieves a stable 3rd-order noise transfer function (NTF) without coefficient scaling. Partial feedback with digital filters is adopted, which only feeds back the 3 MSBs, leading to a fourfold reduction of data-weighted-averaging (DWA) complexity. To mitigate the noise leakage, a gain-boosted two-stage floating inverter amplifier (FIA) with 87.2-dB open-loop gain is proposed with the assistance of the Correlated-level-shifting (CLS) technique. The stability and noise performance of the FIA are also optimized. Fabricated in a 55-nm CMOS process, the prototype analog-to-digital converter (ADC) achieves a measured 93.7-dB signal to noise and distortion ratio (SNDR) in a 10-kHz bandwidth at 800 kS/s at a oversampling ratio (OSR) of 40. With 33.2- mu W power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 178.5 dB and a Walden FoM of 41.9 fJ/conv, demonstrating state-of-the-art energy efficiency. Furthermore, the prototype exhibits fully dynamic characteristics and capabilities to a higher dynamic range (DR).

关键词： Modulation Digital filters Noise Quantization (signal) Gain Topology Energy efficiency Correlated level shifting (CLS) delta-sigma modulator (DSM) floating inverter amplifier (FIA) fully dynamic multi-bit quantizer noise-shaping (NS) successive-approximation-register (NSSAR) partial feedback switched capacitor (SC)

来源：评论

学校读者我要写书评

暂无评论

multi-bit Distributed Detection of Sparse Stochastic Signals Over Error-Prone Reporting Channels

引用

IEEE TRANSACTIONS ON SIGNAL AND INFORMATION PROCESSING OVER NETWORKS 2024年 10卷 881-893页

作者： Mao, Linlin Yan, Shefeng Sui, Zeping Li, Hongbin Chinese Acad Sci Inst Acoust Beijing 100190 Peoples R China Univ Essex Sch Comp Sci & Elect Engn Colchester CO4 3SQ England Stevens Inst Technol Dept Elect & Comp Engn Hoboken NJ 07030 USA

We consider a distributed detection problem within a wireless sensor network (WSN), where a substantial number of sensors cooperate to detect the existence of sparse stochastic signals. To achieve a trade-off between detection performance and system constraints, multi-bit quantizers are employed at local sensors. Then, two quantization strategies, namely raw quantization (RQ) and likelihood ratio quantization (LQ), are examined. The multi-bit quantized signals undergo encoding into binary codewords and are subsequently transmitted to the fusion center via error-prone reporting channels. Upon exploiting the locally most powerful test (LMPT) strategy, we devise two multi-bit LMPT detectors in which quantized raw observations and local likelihood ratios are fused respectively. Moreover, the asymptotic detection performance of the proposed quantized detectors is analyzed, and closed-form expressions for the detection and false alarm probabilities are derived. Furthermore, the multi-bit quantizer design criterion, considering both RQ and LQ, is then proposed to achieve near-optimal asymptotic performance for our proposed detectors. The normalized Fisher information and asymptotic relative efficiency are derived, serving as tools to analyze and compensate for the loss of information introduced by the quantization. Simulation results validate the effectiveness of the proposed detectors, especially in scenarios with low signal-to-noise ratios and poor channel conditions.

关键词： Distributed detection error-prone channels multi-bit quantizer sparse signal wireless sensor networks

来源：评论

学校读者我要写书评

暂无评论

A second-order continuous-time delta-sigma modulator with double self noise coupling

引用

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2019年第2期99卷 251-259页

作者： Yan, Haiyue He, Lin Ye, Yan Lin, Fujiang USTC Micro Nanoelect Syst Integrat R&D Ctr Hefei 230027 Anhui Peoples R China

In this paper, a second-order continuous-time delta-sigma modulator using double self noise coupling technique is proposed. Noise coupling increases the effective order of the noise shaping loops. The presented architecture splits the outputs of the quantizer into a most significant bit segment (MSBs) and a least significant bit segment (LSBs). The LSBs can be viewed as the residue after the MSBs quantization and is fed back to the front of the quantizer and the second integrator respectively, as a result, double self noise coupling is achieved. In addition, the quantizer also provides a convenient means to incorporate the excess-loop-delay compensation. As a result, the digital noise cancellation logic complexity is simplified, the digital and analog filter mismatch is relaxed, meanwhile, it strictly suppresses the noise within the effective signal bandwidth by reducing the main MSBs mismatch. Finally, the resolution is increased, the hardware complexity and the output swing of the integrator are reduced, which greatly relaxes the bandwidth and gain requirement of the Op-Amp design. The higher order noise shaping introduced by the residue of multi-bit quantizer further reduces the quantization noise.

关键词： Second-order Continuous-time Delta-sigma modulator Double self noise coupling (DSNC) Excess-loop-delay (ELD) compensation Digital cancellation Noise shaping loop multi-bit quantizer

来源：评论

学校读者我要写书评

暂无评论

A Two-Phase multi-bit Incremental ADC With Variable Loop Order

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第8期70卷 2724-2728页

作者： Chen, Kaiquan Wang, Biao Liu, Yan Ye, Fan Sin, Sai-Weng Wang, Guoxing Lian, Yong Qi, Liang Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai 200240 Peoples R China Shanghai X Ring Technol Co Ltd Shanghai 201206 Peoples R China Fudan Univ State Key Lab AS & Syst Shanghai 201203 Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China York Univ Dept EECS Toronto ON M3J 1P3 Canada

This brief presents a two-phase multi-bit incremental analog-to-digital converter (IADC) with variable loop order. In the 1(st) phase, the loop filter works as a 1(st)-order topology. In the 2(nd) phase, the loop reconfigures to a 3(rd)-order structure, aiming to get the signal-to-quantization-noise ratio (SQNR) boosted quickly within a few clock cycles. Such a two-phase scheme with variable loop-order combines the features of the KT/C noise suppression and high effectiveness of data weighting averaging (DWA) presented by the 1(st)-order IADC and fast accumulation obtained from the high-order mode. Thereby, with little additional circuitry effort, the proposed IADC improves DWA effectiveness while mitigating the thermal noise penalty when compared with a pure high-order IADC. The proposed architecture is analytically analyzed and exemplarily simulated. Moreover, a design guideline is provided to optimize the allocation of the clock cycles of two phases, thus balancing various significant parameters. Based on the guideline, a circuit-level simulation of an exemplary 1(st)-to-3(rd) order IADC was carried out in a 65-nm CMOS process to confirm the results.

关键词： Incremental ADC variable loop order multi-bit quantizer DWA effectiveness noise penalty

来源：评论

学校读者我要写书评

暂无评论

A High Performance Delta-Sigma Modulator for Neurosensing

引用

SENSORS 2015年第8期15卷 19466-19486页

作者： Xu, Jian Zhao, Menglian Wu, Xiaobo Islam, Md. Kafiul Yang, Zhi Natl Univ Singapore Dept Elect & Comp Engn Singapore 117576 Singapore Univ Minnesota Twin Cities Dept Biomed Engn Minneapolis MN 55455 USA Zhejiang Univ Inst VLSI Design Hangzhou 310027 Zhejiang Peoples R China

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-m CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 W, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

关键词： sensor interface dynamic range multi-bit quantizer switched op-amp Delta-Sigma modulator

来源：评论

学校读者我要写书评

暂无评论

Top-down design methodology of a multi-bit continuous-time delta-sigma modulator

引用

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2009年第1-2期60卷 145-153页

作者： Mariano, A. Dallet, D. Deval, Y. Begueret, J. -B. Univ Bordeaux IMS Lab F-33405 Talence France

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta-sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.

关键词： Analog-to-digital conversion High-IF sampling Continuous-time delta-sigma modulator VHDL-AMS modeling Flash ADC multi-bit quantizer

来源：评论

学校读者我要写书评

暂无评论

Top-down design methodology of a multi-bit continuous-time delta-sigma modulator

Top-down design methodology of a multi-bit continuous-time d...

引用

50th Midwest Symposium on Circuits and Systems

作者： Mariano, A. Dallet, D. Deval, Y. Begueret, J. -B. Univ Bordeaux IMS Lab F-33405 Talence France

关键词： Analog-to-digital conversion High-IF sampling Continuous-time delta-sigma modulator VHDL-AMS modeling Flash ADC multi-bit quantizer

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：