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An attention controlled multi-core architecture for energy efficient object recognition

SIGNAL PROCESSING-IMAGE COMMUNICATION 2010年第5期25卷 363-376页

作者： Kim, Joo-Young Oh, Sejong Lee, Seungjin Kim, Minsu Oh, Jinwook Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Div Elect Engn Sch Elect Engn & Comp Sci Taejon 305701 South Korea

In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing: the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores to perform local object recognition processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of the multiple cores amounts to 92% on average. As a result, the proposed architecture achieves 2.1 x energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87 mJ attention processing. Finally, the proposed architecture is implemented in 0.13 mu m CMOS technology and the fabricated chip verifies 3.2 x lower energy dissipation per frame than the state-of-the-art object recognition processor. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Attention controlled multi-core architecture Object recognition Visual attention Energy efficient

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Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture

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JOURNAL OF SYSTEMS architecture 2017年 74卷 30-45页

作者： Li, Zhenmin Park, Heejong Malik, Avinash Wang, Kevin I-Kai Salcic, Zoran Kuzmin, Boris Glass, Michael Teich, Jurgen Univ Auckland Auckland 1 New Zealand Univ Erlangen Nurnberg Erlangen Germany

The synchronous model of computation is well suited for real-time systems, because it allows static analysis in order to find and guarantee their reaction times. Today's multi-core systems are becoming the predominant computing platforms. Synchronous programs are typically compiled into single threaded code, which makes them unsuitable for exploiting parallelism of the multi-core platforms. Moreover, static timing analysis becomes highly intractable for multi-core systems. This article proposes a novel methodology that aims at finding the mapping and schedule of synchronous programs that guarantees, statically, reaction times when mapped onto a multi-core system consisting of two types of time-predictable cores. The proposed methodology combines design space exploration based on evolutionary algorithm and scheduling of parts of synchronous programs. It allows minimizing the resource usage in terms of number of cores by finding the mapping and schedule with the guaranteed reaction time for architectures with different number of cores. In particular, we: (a) transform a synchronous program written in synchronous System.] to a graph-based model represented with two types of computation nodes suitable for execution on two types of time-predictable cores, (b) perform mapping of computation nodes on a customizable multi-core platform using genetic operations, and (c) generate a resulting static schedule of computation nodes for each mapping as part of the design space exploration. The design flow, from program specification and node mapping to the design space exploration and multi-core scheduling is completely automated. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Synchronous program SystemJ Guaranteed reaction time Design space exploration Evolutionary algorithm Scheduling multi-core architecture

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A robust and scalable multi-level domain decomposition preconditioner for multi-core architecture with large number of cores

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 2020年 373卷

作者： Gratien, Jean-Marc Comp Sci Dept 1 & 4 Bois Preau F-92500 Rueil Malmaison France

With the evolution of High Performance Computing, multi-core and many-core systems are a common feature of new hardware architectures. The required programming efforts induced by the introduction of these architectures are challenging due to the increasing number of cores. Parallel programming models based on the data flow model and the task programming paradigm intend to fix this issue. Iterative linear solvers are a key part of petroleum reservoir simulation as they can represent up to 80% of the total computing time. In these algorithms, the standard preconditioning methods for large, sparse and unstructured matrices such as Incomplete LU Factorization (ILU) or Algebraic multigrid (AMG) fail to scale on shared-memory architectures with large number of cores. multi-level domain decomposition (DDML) preconditioners recently introduced seem to be both numerically robust and scalable on emerging architectures because of their parallel nature. This paper proposes a parallel implementation of these preconditioners using the task programming paradigm with a data flow model. This approach is validated on linear systems extracted from realistic petroleum reservoir simulations. This shows that, given an appropriate coarse operator in such preconditioners, the method has good convergence rates while our implementation ensures interesting scalability on multi-core architectures. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Domain decomposition methods Linear algebra Parallel computing Runtime systems multi-core architecture Reservoir simulation

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ReMCA: A Reconfigurable multi-core architecture for Full RNS Variant of BFV Homomorphic Evaluation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第7期69卷 2857-2870页

作者： Su, Yang Yang, Bai-Long Yang, Chen Zhao, Song-Yin Rocket Force Univ Engn Sch Operat Support Xian 710025 Peoples R China Engn Univ Peoples Armed Police Sch Cryptog Engn Xian 710086 Peoples R China Xi An Jiao Tong Univ Sch Microelect Xian 710049 Peoples R China

Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) for full Residue Number System (RNS) variant of Fan-Vercauteren variant of Brakerski's scheme (RNS-BFV), which employs a variable number of reconfigurable processing elements (PEs) and RNS channels. The PE unit can be flexibly configured as NTT, INTT or modular multiplier, thereby avoiding the need of other extra computational units. To reduce the computational complexity, ReMCA merges the pre/post-processing into NTT/INTT and unifies the read/write structure of NTT and INTT. Also, a conflict-free memory access pattern that doesn't need separate bit-reversal operation is proposed to optimize the memory access. Furthermore, targeting different computational requirements, a unified hardware architecture mapping model and data memory organization model are introduced, and all the computing units that RNS-BFV involved are optimized and mapped on ReMCA. ReMCA is evaluated on a Xilinx Virtex-7 FPGA platform. Running at 250MHz, it can perform 2260 homomorphic multiplication per second. When normalized to the same parameter set, the throughput and Area-Time-Products (ATPs) of ReMCA achieve 1.45x similar to 5.51x and 1.58x similar to 5.12 x improvements.

关键词： Homomorphic encryption reconfigurable PE multi-core architecture NTT/INTT RNS BFV scheme

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A Lock-Controlled Session Table Partitioning Scheme with Dynamic Resource Balancing for multi-core architecture

A Lock-Controlled Session Table Partitioning Scheme with Dyn...

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IEEE International Conference on Communications (ICC)

作者： Tsai, Wen-Yen Huang, Nen-Fu Hung, Hsien-Wei Natl Tsing Hua Univ Inst Commun Engn Hsinchu Taiwan

ISBN: (纸本)9781612842332

Connection tracking by manipulating session tables is essential for stateful inspection capable applications such as stateful firewalls, network-based intrusion prevention systems (NIPS), traffic accounting and monitoring to process packets according to session state information. With the prevalence of multi-core computing, it is crucial to optimize the existing connection tracking structures and algorithms to fully utilize the underlying parallelism. In this paper, we propose a lock-controlled session table partitioning scheme accompanied with a dynamic resource balancing algorithm for session-aware multi-core networking systems. Experimental results show that the proposed scheme reduces the number of lock contentions to a maximum of 100 times less and, in turn, boosts the performance to 3.5 Gbps higher than the baseline. 100% resource utilization is also achieved by overcoming the constraint of fixed-sized partitioning.

关键词： Connection tracking Stateful inspection multi-core architecture

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A multi-core architecture of Digital Back-End for Large Mutual Capacitance Touch Sensing Systems

A Multi-Core Architecture of Digital Back-End for Large Mutu...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yamada, Akihisa Qian, Yan Yamaguchi, Masayuki Honjoh, Hiroshi Morishita, Takahiro Nagasawa, Shunsuke Shinjo, Shinji Miyamoto, Masayuki Sharp Co Ltd Asahi 1Daimon Cho Fukuyama Hiroshima Japan Sharp Co Ltd Tenri Nara Japan

ISBN: (纸本)9781479983919

In this paper, a multi-core architecture suitable for digital back-end processing for medium size or large size mutual capacitance touch sensing systems is proposed. The proposed architecture achieves both high efficiency and flexibility by combining software on CPUs with dedicated circuits for heavy computation tasks, which can realize digital back-end for 10-100 inch touch sensors with the unified architecture. Two ASICs and an FPGA have been implemented and the ASICs are under mass production.

关键词： touch controller digital back-end multi-core architecture

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Composable Platform-Aware Embedded Control Systems on a multi-core architecture 18

Composable Platform-Aware Embedded Control Systems on a Mult...

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18th Euromicro Conference on Digital System Design (DSD)

作者： Valencia, Juan Goswami, Dip Goossens, Kees Eindhoven Univ Technol Elect Syst Grp Eindhoven Netherlands

ISBN: (纸本)9781467380355

In this work, we propose a design flow for efficient implementation of embedded feedback control systems targeted for multi-core platforms. We consider a composable tile-based architecture as an implementation platform and realise the proposed design flow onto one instance of this architecture. The proposed design flow implements the feedback loops in a data-driven fashion leading to time-varying sampling periods with short average sampling period. Our design flow is composed of two phases: (i) representing the timing behaviour imposed by the platform by a finite and known set of sampling periods, which is achieved exploiting the composability of the platform, and (ii) a linear matrix inequality (LMI) based platform-aware control algorithm that explicitly takes the derived platform timing characteristics and the shorter average sampling period into account. Our results show that the platform-aware implementation outperforms traditional control design flows (i.e., almost 2 times) in terms of quality of control (QoC).

关键词： composable embedded control systems lmi-based control multi-core architecture predictable quality of control Quality Control Design flow control systems core construction Platform sampling interval Feedback control systems architecture Building construction time characteristic

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A Spike Vision Approach for multi-object Detection and Generating Dataset Using multi-core architecture on Edge Device 25th

A Spike Vision Approach for Multi-object Detection and Gener...

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25th International Conference on Engineering Applications of Neural Networks (EANN)

作者： Sanaullah Koravuna, Shamini Rueckert, Ulrich Jungeblut, Thorsten Bielefeld Univ Appl Sci & Arts Bielefeld Germany Bielefeld Univ Bielefeld Germany

ISBN: (纸本)9783031624940;9783031624957

Spiking Neural Networks (SNNs) have gained significant attention in the field of neuromorphic computing for their potential to mimic the brain's spiking neurons, allowing event-driven processing based on exact spike timing. In this paper, we introduce a novel architecture that uses the power of SNN in combination with transfer learning to achieve real-time human presence detection and analysis using event-based cameras and compare it with non-event-based cameras. This architecture, which is deployed on edge computing devices, controls a comprehensive pipeline of components, seamlessly integrating various strategies. It combines object detection, transfer learning with SNN, human recognition, localizing and tracking, feature extraction, multi-core architecture, and run-time analysis. The application is initiated by extensively detecting objects and monitoring environments for motion events. Thus, transfer learning adjusts pre-trained Convolutional Neural Network (CNN) weights to SNNs upon detection, enabling event-driven processing. The utilization of multi-core processing speeds up the analytical workload while maintaining real-time operations. The architecture also keeps a valuable spike train dataset, which records important information about recognized objects. This dataset is useful for applications such as behavioral analysis and real-time monitoring.

关键词： Spiking Neural Network NVIDIA Jetson Object Detection Transfer Learning multi-core architecture Real-time Tracking

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Efficient Implementation of Strassen's Algorithm for Memory Allocation using AVX Intrinsic on multi-core architecture 34

Efficient Implementation of Strassen's Algorithm for Memory ...

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34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)

作者： Oo, Nwe Zin Chaikan, Panyayot Prince Songkla Univ Fac Engn Dept Comp Engn Hat Yai 90110 Thailand

ISBN: (纸本)9781728132716

Strassen's algorithm has fascinated as a popular recursive algorithm for square matrix multiplication with the complexity of O(n(2.807)) in many scientific applications since 1969. However, the Strassen's algorithm has the expense of memory allocation as the critical due to the recursive overhead for creating additional temporary storage of submatrices are required. In this paper, the efficient implementation for Strassen's algorithm is proposed by using Advanced Vector Extension (AVX) to optimize the memory allocation with the minimum level of recursive steps suitable for on a multi-core architecture. The experimental results show that Strassen's algorithm can be improved by using AVX and will be effectively multi-threaded by applying OpenMP to boost the performance. The requirement of a huge memory temporary storage for Strassen algorithm is solved and the number of cache hits is increased. Moreover, the performance of Strassen's algorithm utilizing AVX-256 and AVX-512 are respectively 1.8 and 1.7 times faster than the open source library, named Eigen. Our proposed implementation can be applied to all matrix multiplication on the shared memory computers that use Strassen's algorithm at the system level for high performance computing.

关键词： AVX memory allocation OpenMP Strassen's algorithm shared memory multi-core architecture

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High-Performance Video Based Fire Detection Algorithms Using a multi-core architecture

High-Performance Video Based Fire Detection Algorithms Using...

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7th International Conference on Intelligent Computing (ICIC)

作者： Kim, Yongmin Kang, Myeongsu Kim, Jong-Myon Univ Ulsan Sch Elect Engn Ulsan 680749 South Korea

ISBN: (纸本)9783642259432

As fire accidents usually cause economic and environmental damage, including the loss of human lives, video-based fire detection has become more appealing in surveillance systems. However, video based fire detection algorithms demand tremendous computational and I/O requirements. To meet these requirements, we introduce an SIMD (Single Instruction multiple Data) based multi-core architecture that consists of 16 processing elements (PEs) and small local memory. In addition, we compare the performance and efficiency of the multi-core architecture with a commercial Texas Instrument digital signal processor (TI DSP) to demonstrate the potential for improved performance of the multi-core architecture. Experimental results indicate that the multi-core architecture is 27.18 times and 3.89 times better than TI DSP in terms of execution time and energy efficiency, respectively.

关键词： multi-core architecture fire detection algorithms parallel processing

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