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A Practical Cache Partitioning Method for multi-core processor on a Commercial Safety-Critical Partitioned RTOS

IEEE ACCESS 2025年 13卷 25505-25519页

作者： Kim, Taeho Seoul Womens Univ Informat Secur Div Seoul 01797 South Korea

In modern airborne systems, software plays a crucial role for meeting functional, safety, and performance requirements. Integrated Modular Avionics (IMA) and multi-core processors (MCPs) are also adopted for hardware to enhance performance and Space, Weight, and Power (SWaP). While MCPs improve efficiency, they introduce nondeterministic behaviors due to resource contention and challenges for the safety of avionics systems. This research proposes a practical cache partitioning method for commercial Real-Time Operating Systems (RTOS) on MCPs to reduce cache contention and enhance the safety and performance of avionics systems. A systematic procedure was developed based on DO-178 and CAST 32A to identify shared resources and prevent interference. Additionally, we developed a cache partitioning guide tool to decide the optimal cache partition for each application. This research demonstrated that shared L2 caches could cause severe performance degradation up to 88% using the WindRiver VxWorks 653 on the PowerPC T2080 processor. By applying the proposed partitioning technique, the system achieved 0% performance degradation, eliminating cache contention and ensuring consistent application performance. The partitioning approach also ensured deterministic application behavior, a critical requirement for safety-critical systems. Validation in a flight simulation environment confirmed the practicality of the method in real-world scenarios.

关键词： Aerospace electronics Software Operating systems Interference Safety multicore processing Hardware Object recognition Real-time systems Computer architecture Avionics real-time operating systems cache partitioning safety-critical systems multi-core processor

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multi-core processor Scheduling Algorithm under The Influence Of Process Variation 18

Multi-Core Processor Scheduling Algorithm under The Influenc...

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2nd International Conference on Algorithms, Computing and Systems (ICACS)

作者： Wei, Xiaohui Su, Lishuang Tan, Jingweijia Jilin Univ JLU Coll Comp Sci & Technol Changchun Jilin Peoples R China

ISBN: (纸本)9781450365093

Due to process variation, different cores of multi-core processors will generate frequency heterogeneity, and the difference in frequency will cause difference in the speed of executing instructions. The existing multi-core processor scheduling algorithms do not take the process variation into account, and ignore the deviation in the manufacturing process. This paper proposes a frequency-heterogeneous scheduling algorithm MFF (Max-Fast-First), which allocates long time-consuming tasks to cores with high frequency and assigns short time-consuming tasks to cores with low frequency, thus shortening the total operation time. The experimental results show that the MFF algorithm reduces the running time by 17.87% compared to the dynamic Min-Min algorithm, and it reduces the running time by 9.10% compared to the CATS(Criticality-Aware Task Scheduler) algorithm. At the same time, the running time of the MFF algorithm is less affected by the process variation, which is better than dynamic Min-Min and CATS to process variation.

关键词： frequency heterogeneity multi-core processor scheduling process variation

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Energy Efficiency of a multi-core processor by Tag Reduction

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Journal of Computer Science & Technology 2011年第3期26卷 491-503页

作者：郑龙董冕雄 Kaoru Ota 金海 Song Guo 马俊 School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China School of Computer Science and Engineering The University of Aizu Aizu-Wakamatsu 965-8580 Japan Department of Electrical and Computer Engineering University of Waterloo N2L 3G1 Canada Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai 200240 China

We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

关键词： tag reduction multi-core processor energy efficiency

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A Heuristic Task Periods Selection Algorithm for Real-Time Control Systems on a multi-core processor

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IEEE ACCESS 2017年 5卷 24819-24829页

作者： Fu, Hongya Liu, Jiankang Han, Zhenyu Shao, Zhongxi Harbin Inst Technol Sch Mechatron Engn Harbin 150001 Heilongjiang Peoples R China

The performance optimization problem is investigated for discrete-time control systems on a multi-core platform. An integrated approach which considers both control performance and real-time scheduling aspects is applied to allocate optimal periods to controller tasks. A real-time control system is modeled as a set of directed acyclic graphs with weighted edges in this paper. The system allows producer/consumer relationship between tasks, and the data dependence relationships between tasks are uncoupled by attaching harmonic constraints to task periods. The period assignment problem is formulated as an optimization problem, which minimizes the system performance loss index under multi-core schedulability constraints. A heuristic search algorithm is proposed to solve this optimization problem and select periods for real-time tasks scheduled by rate-monotonic scheduling algorithm. Experimental results demonstrate that the proposed heuristic algorithm is capable of finding a high quality local optimal solution with fast computing speed. The proposed method is applicable to online failure recovery and reconfiguration in real-time control systems.

关键词： Control systems multi-core processor performance optimization period selection real-time control system

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A multi-core processor BASED REAL-TIME multi-MODAL EMOTION EXTRACTION SYSTEM EMPLOYING FUZZY INFERENCE

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INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL 2011年第8期7卷 4603-4620页

作者： Sato, Yoshiki Miki, Tsutomu Honda, Keiichiro Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku Kitakyushu Fukuoka 8080196 Japan

Recently, researchers have paid close attention to human emotions to develop intelligent human-machine interfaces. Emotion extraction that considers only a single modality, however, has limitations, because each modality has its own weaknesses with respect to different emotions. multi-modal sensing that mimics that employed by humans is, therefore, very important to improve extraction performance. We propose a multi-modal emotion extraction system based on fuzzy inference that is understandable to human beings. The system has a module-based hierarchical architecture in which the lower module handles emotion extraction independently for each modality, while the upper module integrates the results for all the modalities. Parallel processing is necessary for real-time processing of the multi-modal emotion extraction. We have implemented the proposed system on a multi-core processor, the "Cell Broadband Engine (TM)" with multiple cores specialized for stream data processing. In this paper, we demonstrate the multi-modal emotion extraction system with two modalities, namely facial expressions and voice. Furthermore, to improve system performance, we propose a method to optimize fuzzy rules for facial expressions and voice using SOM clustering and statistical methods, respectively. The performance and validity of the proposed system, are discussed based on the experimental results for emotion extraction of six basic emotions.

关键词： Emotion extraction Fuzzy inference multi-modal sensing multi-core processor

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S2MSim: Cycle-Accurate and High-Performance Simulator Based on multi-Threading for Space multi-core processor

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INTERNATIONAL JOURNAL OF AERONAUTICAL AND SPACE SCIENCES 2023年第5期24卷 1465-1478页

作者： Jeong, Jae-Yeop Lee, Cheol-Hoon Korea Aerosp Res Inst Satellite Technol Res & Dev Div 169-84 Gwahak Ro Daejeon 34133 South Korea Chungnam Natl Univ Dept Comp Sci & Engn 99 Daehak Ro Daejeon 34134 South Korea

A processor simulator is an essential tool for developing, testing, and verifying flight software in the space domain;this tool should be capable of correctly simulating a space-grade processor with high performance and cycle-accuracy. Existing space simulators typically use single-thread-based interpretation methods to satisfy these requirements. Since these methods involve sequential core execution by a single thread, which degrades the overall performance and cycle-accuracy, they are unsuitable for multi-core processor simulations. In this study, we propose a cycle-accurate and high-performance multi-core processor simulator based on multi-threading called the Scalable processor Architecture multi-core multi-threading simulator (S2MSim) which accurately models the working of the GR740 quad-core processor through three schemes. First, we assigned each GR740 core to a host thread to improve the performance and dynamically allocated a simulator manager to these specific host threads to minimize the overhead induced by thread communications. Second, we analyzed the inter-core interference effects and reflected the results required for each core to achieve a high cycle-accuracy. Finally, we used a fine-grained lock to provide the simulated cores with simultaneous access to shared resources and spin-lock to thread synchronization. The experimental results showed that on an average, the S2MSim could run 3.09 and 4.18 times faster than TSIM3-LEON4 and laysim-gr740, respectively. We achieved a high cycle-accuracy within a +/- 3% error margin compared to that shown by the GR740 development board from Cobham Gaisler AB.

关键词： GR740 Parallel simulator Flight software multi-core processor Cycle-accuracy

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A comparison of 3D cone-beam Computed Tomography (CT) image reconstruction performance on homogeneous multi-core processor and on other processors

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MEASUREMENT 2011年第10期44卷 2035-2042页

作者： Chen, Szi-Wen Chu, Chang-Yuan Chang Gung Univ Dept Elect Engn Tao Yuan 333 Taiwan

Computed Tomography (CT) has become an important noninvasive tool in diagnostic medicine. In fact, the use of cone-beam CT is growing in the clinical area due to its ability to provide 3D volumetric information. This study aims to parallelize an analytical 3D image reconstruction algorithm and then implement it on a commercial homogeneous multi-core processor. It is indicated from our results that the homogeneous multi-core processor actually achieved faster reconstruction than the heterogeneous processor-based or the FPGA-based implementation. Our results demonstrated that the shared cache mechanism associated with the homogeneous processor would represent a significant benefit to performing high-speed CT reconstruction or other High Performance Computing (HPC) applications. In addition, while the Graphic Processing Unit (GPU) is considered the most powerful processor nowadays, our experimental results further indicated that the joint use of the multi-core CPU and CPU could enhance the processing power as well as improve the computational efficiency. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： Computed Tomography (CT) Graphic Processing Unit (GPU) Hardware acceleration 3D reconstruction multi-core processor Parallel processing

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A Novel Task Partitioning Method for multi-core processor Based-on Cohesion and Coupling

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JOURNAL OF COMPUTERS 2013年第5期8卷 1247-1254页

作者： Jiang, Jianchun Zeng, Suhua Chongqing Univ Posts & Telecommun Coll Automat Chongqing 400065 Peoples R China Chongqing Univ Posts & Telecommun Sch Comp Sci & Technol Chongqing 400065 Peoples R China

Task partition is a NP-Hard problem on multi-core processor. To achieve a good MCT (maximum completion time) goal, this paper presents a novel task partitioning method for multi-core processor based on the cohesion and coupling properties of tasks. First, the relations between the cohesion and coupling are analyzed and the computation method of coupling cost based on cohesion is designed with the task scheduling requirements considered. Then, aiming to the problem that the MCT (maximum completion time) is different when the tasks' coupling is changed and the tasks are rescheduled during the task partitioning process, an evaluating method of MCT with the considering of task scheduling requirements is designed. Last, this paper compartmentalizes tasks based on the MCT to make it minimum. This method reduces the processing of the combinatorial optimization problem in task partitioning process, and builds the relation between task partition and task scheduling. The experimental results testify this method available.

关键词： multi-core processor Task Partition Cohesion Coupling

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Exploring parallelization techniques based on OpenMP in H.264/AVC encoder for embedded multi-core processor

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JOURNAL OF SYSTEMS ARCHITECTURE 2012年第9期58卷 339-353页

作者： Jo, Seongmin Jo, Song Hyun Song, Yong Ho Hanyang Univ Dept Elect & Commun Engn Seoul 133791 South Korea Hanyang Univ Dept Elect & Comp Engn Seoul 133791 South Korea

Recent advances in semiconductor technologies make it possible to integrate many processor cores in a small device package. The parallel execution capability of such multi-core processors can be exploited to enhance the performance of many traditional sequential applications. There have been numerous research activities to develop parallelization techniques using the OpenMp programming model, in order to speed up sequential applications such as the H.264/AVC codec, but mostly in the PC environment. Therefore, it is difficult to understand which parallelization technique fits well with the H.264/AVC encoder on an embedded multi-core architecture. In this paper, we present parallelization techniques applicable to the H.264/AVC encoder on ARM MPcore using the OpenMP programming model. Further, we propose an analytical model for the performance estimation of the H.264/AVC encoder, and we then verify the model accuracy by performing simulations using hardware/software co-verification tool. Our experimental results show that the parallelization techniques proposed in this paper for the embedded multi-core platform improve the encoder performance by up to 2.36 times, and that the parallelization technique exploiting data-level parallelism outperforms the one using task-level parallelism by 41%. It is also observed that balancing loads among processor cores is a critical parameter in achieving better scalability in the encoder. (c) 2012 Elsevier B.V. All rights reserved.

关键词： Parallel programming multimedia codec multi-core processor Embedded system Design exploration

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The Compatibility Analysis of Thread Migration and DVFS in multi-core processor

The Compatibility Analysis of Thread Migration and DVFS in M...

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11th International Symposium on Quality Electronic Design (ISQED)

作者： Oh, Dongkeun Chen, Charlie Chung Ping Kim, NamSung Hu, Yu Hen Univ Wisconsin Madison WI 53706 USA Natl Taiwan Univ Taipei Taiwan

ISBN: (纸本)9781424464555

Integrating multiple cores into a processor increases the heat density significantly, which often constrains the maximum performance of such a processor. There have been many techniques using dynamic voltage and frequency scaling (DVFS) and thread migration to manipulate heat dissipation in thermally-constrained multi-core processors. However, most of them were analyzed and applied individually for optimizing the performance of the multi-core processors while their computational cost for the optimization was not studied well. In this paper, we argue that a coherent organization of two techniques can maximize the performance of the multi-core processors with the least performance overheads associated with the thermal management techniques. Furthermore, we also propose an efficient method to optimize the performance of thermal-constrained multi-core processors. According to our experiment, we achieved 5% throughput improvement with negligible computation cost.

关键词： multi-core processor thermal simulation dynamic voltage and frequency scaling thread-migration

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