检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3 篇 会议

馆藏范围

3 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2 篇 工学
- 2 篇 计算机科学与技术...
- 1 篇 电气工程

主题

3 篇 multi-fpga based...
2 篇 multi-gigabit tr...
2 篇 inter-fpga commu...
1 篇 performance
1 篇 iserdes/oserdes
1 篇 cabling
1 篇 hardwired off-th...
1 篇 logic multiplexi...
1 篇 custom

机构

2 篇 univ paris 06 la...
2 篇 flexras technol
1 篇 flexras technolo...
1 篇 université pierr...

作者

2 篇 mehrez habib
2 篇 tang qingshan
2 篇 tuna matthieu
1 篇 matthieu tuna
1 篇 habib mehrez
1 篇 qingshan tang

语言

3 篇 英文

检索条件"主题词=multi-fpga based prototyping"

共 3 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Future inter-fpga communication architecture for multi-fpga based prototyping (abstract only) 14

Future inter-FPGA communication architecture for multi-FPGA ...

引用

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

作者： Qingshan Tang Matthieu Tuna Habib Mehrez Université Pierre et Marie CURIE Paris France Flexras Technologies Paris France

ISBN: (纸本)9781450326711

multi-fpga boards are widely used for rapid system prototyping. Even though the prototyping is trying to reach the maximum performance, the performance is limited by the inter-fpga communication. As the capacity per I/O for each fpga generation is increasing, fpga I/Os are becoming a scarce resource. The design is divided into several parts, each part's capacity fits in a single fpga. Signals crossing design's parts located in different fpgas are called cut nets. In order to resolve pin limitation problem, cut nets are sent between fpgas in pipelined way using the Time-Division-multiplexing technique. The maximum number of cut nets passing through one fpga I/O is called the TDM ratio. There are two multiplexing architectures used for multi-fpga based prototyping: Logic multiplexing and ISERDES/OSERDES. In this paper, a new multiplexing architecture multi-Gigabit Transceiver (MGT) is proposed. Experiments are done in a multi-fpga board with the testbench LFSR to validate the achieved performance. Assume that all the fpga I/Os used for inter-fpga communication are MGT capable in the future. Analyses show that the proposed multiplexing architecture can achieve higher performance when the TDM ratio exceeds 67. The gain in performance of the proposed architecture over the existing architecture augments as the TDM ratio increases.

关键词： multi-fpga based prototyping logic multiplexing inter-fpga communication iserdes/oserdes multi-gigabit transceiver

来源：评论

学校读者我要写书评

暂无评论

Performance Comparison between multi-fpga prototyping Platforms: Hardwired Off-the-Shelf, Cabling and Custom 22

Performance Comparison between Multi-FPGA Prototyping Platfo...

引用

22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines ((FCCM)

作者： Tang, Qingshan Mehrez, Habib Tuna, Matthieu Univ Paris 06 Lab Informat Paris 6 Paris France Flexras Technol Paris France

ISBN: (纸本)9781479951116

We can classify multi-fpga prototyping platforms in three categories: hardwired off-the-shelf, cabling and custom. Three points are developed in this paper. Firstly, an automatic design flow is proposed to generate a cabling platform and a custom platform for a given design. Then, the optimal width of cables for a cabling multi-fpga platform is explored. Finally, the performances of these three multi-fpga platforms are compared. The results show that the cabling platform achieves up to 82% gain in performance, and the custom platform achieves up to 100%, compared to the hardwired off-the-shelf platform. The custom platform achieves up to 20% gain in performance over the cabling platform. Therefore the results show that, apart from some stringent constraints (such as deployment cost or specific frequency needed), the relatively new cabling paradigm with the proposed automatic, inter-fpga tracks distribution tool, offers an attractive alternative compared to the two other platforms.

关键词： multi-fpga based prototyping Hardwired Off-the-Shelf Cabling Custom Performance

来源：评论

学校读者我要写书评

暂无评论

multi-fpga prototyping Board Issue: the fpga I/O Bottleneck 14

Multi-FPGA Prototyping Board Issue: the FPGA I/O Bottleneck

引用

International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Tang, Qingshan Mehrez, Habib Tuna, Matthieu Univ Paris 06 Lab Informat Paris 6 Paris France Flexras Technol Paris France

ISBN: (纸本)9781479937707

multi-fpga boards are widely used for rapid system prototyping. As the ratio between the logic capacity and the number of U0s for each fpga generation is increasing, fpga U0s are becoming a scarce resource. In order to resolve pin limitation problem, cut nets are sent between fpgas in a pipelined way using the Time-Division-multiplexing technique. The maximum number of cut nets passing through one fpga I10 is called the TDM ratio. There are three inter-fpga communication architectures: Logic multiplexing, ISERDES/OSERDES and multi-Gigabit Transceiver (MGT). Only Logic multiplexing and ISERDES/OSERDES are today used for Time-Division-multiplexing in the multi-fpga based prototyping. In this paper, the achieved performance of Logic multiplexing and ISERDES/OSERDES is compared in different TDM ratios and a hybrid multiplexing architecture using both ISERDES/OSERDES and MGT is proposed. Experiments are done in a multi-fpga board with the testbench LFSR to validate the achieved performance. The results show that even though consuming more fpga U0s for data transmission, ISERDES/OSERDES can achieve higher performance than Logic multiplexing. The proposed architecture can achieve higher performance than ISERDES/OSERDES when the TDM ratio exceeds 54. The maximum gain in performance is about 20%.

关键词： multi-fpga based prototyping Inter-fpga Communication multi-Gigabit Transceiver

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共1页 << < 1 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：