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Unifying Fixed Code Mapping, Communication, Synchronization and scheduling Algorithms for Efficient and Scalable Loop Pipelining

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2018年第9期29卷 2136-2149页

作者： Mastoras, Aristeidis Gross, Thomas R. Swiss Fed Inst Technol Dept Comp Sci CH-8092 Zurich Switzerland

Pipelining allows the execution of loop iterations with cross-iteration dependences to overlap in time, provided that the loop body is partitioned into stages such that the data dependences are not violated. Then, the stages are mapped onto threads and communication and synchronization between stages is typically achieved using queues. Pipelining techniques that rely on static scheduling perform poorly for load-imbalanced loops. Moreover, previous research efforts that achieve load-balancing are restricted to work-stealing and imply high overhead for fine-grained loops. In this article, we present URTS, a unified runtime system with compiler support that provides a lightweight dynamic scheduler by combining mapping, communication and synchronization algorithms with a suitable data structure and an efficient ticket mechanism. Particularly, URTS shows that it is possible to combine the efficiency of static scheduling with the load-imbalance tolerance of work-stealing by using a unified design that exploits the properties of a novel data structure. The evaluation on 8- and 32-core machines shows that URTS implies low overhead, of the same order as a static scheduler, for a set of benchmarks chosen from widely-used collections. URTS is a scalable solution that performs efficient dynamic scheduling for fine-grained loops, i.e., a class of interesting loops that is poorly handled by the state-of-the-art due to high overhead.

关键词： Linear pipeline partitioning fixed code mapping communication synchronization multi-threading: dynamic scheduling parallelization directives runtime system

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Efficient and Scalable Execution of Fine-Grained dynamic Linear Pipelines

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2019年第2期16卷 8-8页

作者： Mastoras, Aristeidis Gross, Thomas R. Swiss Fed Inst Technol Dept Comp Sci CH-8092 Zurich Switzerland

We present Pipelite, a dynamic scheduler that exploits the properties of dynamic linear pipelines to achieve high performance for fine-grained workloads. The flexibility of Pipelite allows the stages and their data dependences to be determined at runtime. Pipelite unifies communication, scheduling, and synchronization algorithms with suitable data structures. This unified design introduces the local suspension mechanism and a wait free enqueue operation, which allow efficient dynamic scheduling. The evaluation on a 44-core machine, using programs from three widely used benchmark suites, shows that Pipelite implies low overhead and significantly outperforms the state of the art in terms of speedup, scalability, and memory usage.

关键词： dynamic linear pipeline dynamic partitioning dynamic communication dynamic synchronization multi-threading: dynamic scheduling parallelization directives

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Unifying Fixed Code and Fixed Data Mapping of Load-Imbalanced Pipelined Loops 16

Unifying Fixed Code and Fixed Data Mapping of Load-Imbalance...

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21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Mastoras, Aristeidis Gross, Thomas R. ETH Dept Comp Sci CH-8092 Zurich Switzerland

ISBN: (纸本)9781450340922

Some loops with cross-iteration dependences can execute in parallel by pipelining. The loop body is partitioned into stages such that the data dependences are not violated and then the stages are mapped onto threads. Two well-known mapping techniques are fixed code and fixed data;they achieve high performance for load-balanced loops, but they fail to perform well for load-imbalanced loops. In this article, we present a novel hybrid mapping that eliminates drawbacks of both prior mapping techniques and enables dynamic scheduling of stages.

关键词： pipeline model mapping multi-threading: dynamic scheduling

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