检索结果-内蒙古大学图书馆

IEEE 13th International Symposium on Embedded multicore/Many-Core Systems-on-Chip (MCSoC)

作者： Kuan, Kyle Adegbija, Tosiron Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781728148823

Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics-and hence, STTRAM cache design requirements-differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.

关键词： Spin-Transfer Torque RAM (STTRAM) cache mobile applications performance analysis retention time non-volatile memory energy efficient multicore processor

来源：评论

学校读者我要写书评

暂无评论

AN APPLICATION BASED EFFICIENT THREAD LEVEL PARALLELISM SCHEME ON HETEROGENEOUS multicore EMBEDDED SYSTEM FOR REAL TIME IMAGE PROCESSING

引用

SCALABLE COMPUTING-PRACTICE AND EXPERIENCE 2020年第1期21卷 47-56页

作者： Indragandhi, K. Jawahar, P. K. BS Abdur Rahman Crescent Inst Sci & Technol Chennai Tamil Nadu India

The recent advent of the embedded devices is equipped with multicore processor as it significantly improves the system performance. In order to utilize all the core in multicore processor in an efficient manner, application programs need to be parallelized. An efficient thread level parallelism (ETLP) scheme is proposed in this paper and uses computationally intensive edge detection algorithm for evaluation. Edge detection is the important process in various real time applications namely vehicle detection in traffic control, medical image processing etc. The main objective of ETLP scheme is to reduce the execution time and increase the CPU core utilization. The performance of ETLP scheme is evaluated with basic edge detection scheme (BEDS) for different image size. The experimental results reveal that the proposed ETLP scheme achieves efficiency of 49% and 72% for the image size 300 x 256 and 1024 x 1024 respectively. Furthermore an ETLP scheme reducing 66% execution time for image size 1024 x 1024 when compared with BEDS.

关键词： Heterogeneous multicore processor Image processing Edge Detection CPU utilization

来源：评论

学校读者我要写书评

暂无评论

A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of multicore Architecture 20

A New Approach to Guarantee Critical Task Schedulability in ...

引用

20th IEEE Latin American Test Symposium (LATS)

作者： Lara, Estevan Debon, Guilherme Goerl, Roger Villa, Paulo Schramm, Dorian Poehls, Leticia B. Vargas, Fabian Catholic Univ PUCRS Elect Engn Dept Porto Alegre RS Brazil Fed Inst Rio Grande Do Sul IFRS Rio Grande Do Sul Brazil

ISBN: (纸本)9781728117560

The use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase in recent years. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources, which severely degrades the timing predictability of multicore software due to the bus access contention between cores. To counteract this problem, we present in this paper a new approach that supports mixed-criticality workload execution in a multicore processor-based embedded system. It allows any number of cores to run less-critical tasks concurrently with the critical core, which is running the critical task. The approach is based on the use of an infrastructure intellectual property (I-IP) core named Deadline Enforcement Checker (DEC) implemented in hardware, which allows the execution of any number of cores (running less-critical workloads) concurrently with the critical core (executing the critical workload). This approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability, i.e., that the critical task execution will not violate timing deadline. A case-study based on a dual-core version of the LEON3 softcore processor was implemented in VHDL language. Practical experiments demonstrate the proposed technique is very effective on combining system high performance with critical task schedulability within timing deadline.

关键词： multicore processor Critical application High-performance embedded system Critical task schedulability Worst-Case Execution Time (WCET) Mixed criticality workload execution Deadline violation

来源：评论

学校读者我要写书评

暂无评论

Maximizing Common Idle Time on multicore processors With Shared Memory

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017年第7期25卷 2095-2108页

作者： Fu, Chenchen Zhao, Yingchao Li, Minming Xue, Chun Jason City Univ Hong Kong Dept Comp Sci Hong Kong Hong Kong Peoples R China Caritas Inst Higher Educ Sch Comp & Informat Sci Hong Kong Hong Kong Peoples R China

Nowadays, memory energy reduction attracts significant attention as main memory consumes large amount of energy among all the energy consuming components. This paper focuses on reducing the energy consumption of the shared main memory in multicore processors by putting the memory into sleep state when all cores are idle. Based on this idea, we present systematic analysis of different models and propose a series of scheduling schemes to maximize the common idle time of all cores. The target problem is classified into two cases based on whether task migration is allowed or not among cores. Considering task migration, an optimal scheduling scheme is proposed, assuming the number of cores is unbounded. When the number of cores is bounded, an integer linear programming formulation and two efficient heuristic algorithms are proposed. When task migration is not allowed, we first prove the NP-hardness of the problem, and then propose the optimal solutions when task partitions are given in advance. The energy overhead caused by transitions between active and sleep modes of the memory is analyzed. The experimental results show that the heuristic algorithms work efficiently and can save 7.25% and 11.71% system energy, respectively, with 1-GB memory, compared with an energy-efficient multicore scheduling scheme. Larger energy reduction can be further achieved with larger size of memory.

关键词： Energy efficiency multicore processor real-time task scheduling algorithms shared main memory

来源：评论

学校读者我要写书评

暂无评论

Countering power analysis attacks by exploiting characteristics of multicore processors

引用

IEICE ELECTRONICS EXPRESS 2018年第7期15卷 20180084-20180084页

作者： Yang, Jianwei Dai, Fan Wang, Jielin Zeng, Jianmin Zhang, Zhang Han, Jun Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China Hefei Univ Technol Sch Elect Sci & Appl Phys 193 Tunxi Rd Hefei 230009 Anhui Peoples R China

Power analysis attacks are major concerns among all kinds of side channel attacks. This paper proposes three kinds of countermeasures for Differential Power Analysis (DPA) attacks by fully exploiting characteristics of a many-core processor: (1) Data-level parallelism, (2) Random Dynamic Task Scheduling (RDTS), and (3) Random Dynamic Adjustment (RDA), which combines RDTS, Random Dynamic Frequency Scaling (RDFS) and Random Dynamic Phase Adjustment (RDPA). For the first time these techniques are applied to a multicore processor from the perspective of secure system design. AES algorithm with mentioned countermeasures is implemented on an 8-core processor. Simulation results show that these countermeasures considerably improve the system security with little performance overhead.

关键词： DPA CPA multicore processor

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Instruction-Based multicore Parallel Convolution and Its Application in Real-Time Template Matching

引用

IEEE TRANSACTIONS ON COMPUTERS 2018年第12期67卷 1780-1793页

作者： Zhou, Quan Yang, Liang Yan, Xin Ninth Acad China Aerosp Sci & Technol Corp Xian Microelect Technol Inst Xian Shaanxi Peoples R China

Convolution is widely used in scientific computational fields such as digital image processing and machine learning. However, these applications are difficult to execute in realtime because they are computationally intensive. This paper introduces a high-speed convolution solution that runs on our self-developed multicore digital signal processor (DSP). To optimize the convolution capability, we propose a convolution instruction and a convolution micro architecture in the design of a subcore. As a coprocessor, the designed subcore is integrated into a network-on-chip (NoC)-based multicore DSP. In the implementation of the multicore parallel convolution, an independent convolution task-partitioning and mapping scheme is proposed. Datablock storage and software prefetching mechanisms are used to hide the data transmission time during the calculation, improving the computing efficiency. We also develop a data reuse strategy that effectively reduces the data bandwidth requirements of multicore parallel convolution. The proposed methods are applied to correlation-based template matching, with the results showing that our convolution computing approach greatly improves the performance compared with the same operations run on a personal computer, a TMS320C6678 processor and an NVIDIA Quadro 1000M graphics processing unit (GPU).

关键词： Convolution cross-correlation multicore processor parallel computing reconfigurable instruction template matching

来源：评论

学校读者我要写书评

暂无评论

Analysis of Power Management Techniques in multicore processors

引用

International Conference on Artificial Intelligence and Evolutionary Computations in Engineering Systems (ICAIECES)

作者： Nagalakshmi, K. Gomathi, N. Hindusthan Inst Technol Dept Comp Sci & Engn Coimbatore Tamil Nadu India Vel Tech Dr RR & Dr SR Univ Dept Comp Sci & Engn Madras Tamil Nadu India

ISBN: (纸本)9789811031748;9789811031731

Power and performance have become significant metrics in the designing of multicore processors. Due to the ceasing of Moore's law and Dennard scaling, reducing power budget without compromising the overall performance is considered as a predominant limiting factor in multicore architecture. Of late technological advances in power management techniques of the multicore system substantially balance the conflicting goals of low power, low cost, small area, and high performance. This paper aims at ascertaining more competent power management techniques for managing power consumption of multicore processor through investigations. We highlight the necessity of the power management techniques and survey several new approaches to focus their pros and cons. This article is intended to serve the researchers and architects of multicore processors in accumulating ideas about the power management techniques and to incorporate it in near future for more effective fabrications.

关键词： multicore processor Power management DVFS Clock gating Task scheduling Task migration

来源：评论

学校读者我要写书评

暂无评论

Load Balancing of multicore Systems using Heuristics

Load Balancing of Multicore Systems using Heuristics

引用

International Conference on Computing, Power and Communication Technologies (GUCON)

作者： Jadon, Shruti Yadav, Rama Shankar Motilal Nehru Natl Inst Technol Allahabad Uttar Pradesh India

ISBN: (纸本)9781538644911

multicore processing is increasing rapidly as the single core processors are unable to meet the demands of highly advanced time critical applications. The tasks in such real time applications require the jobs to meet their deadlines. The proposed paper discusses about the heuristic based load balancing (HBLB) algorithm such that workload is equal amongst all the cores in the processor which results in increased utilization and computing speed of the application with all the deadlines met. The heuristic based load balancing algorithm selects the best task from the task set using the feasibility check window and assigns it to the core. The algorithm results in reduced imbalance among the cores and less number of migrations which further result in low migration overhead. Utilizing all the cores of the multicore system will result in high computing speed to the application, hence increasing the efficiency of the system.

关键词： multicore processor imbalance load balancing heuristics real time systems

来源：评论

学校读者我要写书评

暂无评论

Increasing System Performance in Machine Learning by using Multiprocessing 26

Increasing System Performance in Machine Learning by using M...

引用

26th IEEE Signal Processing and Communications Applications Conference (SIU)

作者： Ozan, Sukru AdresGezgini AS Ar Ge Merkezi Folkart Towers BKule Ofis 3609 Bayrakli Izmir Turkey

ISBN: (纸本)9781538615010

Machine Learning regained its popularity after the recent advances occurred in deep learning area and Python programming language is increasingly being used in machine learning. It is important to choose proper initial values for variables called hyper parameters used in machine learning. Selecting proper initial values for these variables directly effects the systems performance at the training, testing and validation steps of learning model. In some situations optimal initial values for hyper parameters are found by trial method. This means that so many trials may need to be performed and these trials consumes much lower time once the computers multiprocessing feature is used. In this work, it is shown how some operations which may be needed in machine learning methods are performed on more than one processor by using simple scripts written in Python programming language. Moreover the time gain obtained with these scripts is calculated.

关键词： python programming language machine learning multicore processor multiprocessing

来源：评论

学校读者我要写书评

暂无评论

Parallel Solutions to the k-difference Primer Problem 18th

Parallel Solutions to the <i>k</i>-difference Primer Problem

引用

18th International Conference on Computational Science (ICCS)

作者： Feuser, Leandro Moreano, Nahri Univ Fed Mato Grosso do Sul Sch Comp Campo Grande MS Brazil

ISBN: (纸本)9783319936987;9783319936970

This paper presents parallel solutions to the k-difference primer problem, targeting multicore processors and GPUs. This problem consists of finding the shortest substrings of one sequence with at least k differences from another sequence. The sequences found in the solution are candidate regions to contain primers used by biologists to amplify a DNA sequence in laboratory. To the authors' knowledge, these are the first parallel solutions proposed for the k-difference primer problem. We identified two forms, coarse- and fine-grained, of exploiting parallelism while solving the problem. Several optimizations were applied to the solutions, such as synchronization overhead reduction, tiling, and speculative prefetch, allowing the analysis of very long sequences in a reduced execution time. In an experimental performance evaluation using real DNA sequences, the best OpenMP (in a quad-core processor) and CUDA solutions produced speedups up to 5.6 and 72.8, respectively, when compared to the best sequential solution. Even when the sequences length and the number of differences k increase, the performance is not affected. The best sequential, OpenMP, and CUDA solutions achieved the throughput of 0.16, 0.94, and 11.85 billions symbol comparisons per second, respectively, emphasizing the performance gain of the CUDA solution, which reached 100% of GPU occupancy.

关键词： Inexact matching High performance computing Parallelism multicore processor GPU

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：