An automatic synthesis system for PLA based programmable hardware as part of a VLSI design system is presented. In order to reduce the needed silicon area of a PLA implementation we suggest algorithms for segmentation...
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An automatic synthesis system for PLA based programmable hardware as part of a VLSI design system is presented. In order to reduce the needed silicon area of a PLA implementation we suggest algorithms for segmentation, term minimization and PLA — folding. We present results of the implemented term minimization and PLA-folding procedures.
Cost functions for combinational switching circuits are commonly defined as monotonically increasing functions of the number of gates and the number of inputs. The structure of programmable logic arrays (PLA's) is...
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Cost functions for combinational switching circuits are commonly defined as monotonically increasing functions of the number of gates and the number of inputs. The structure of programmable logic arrays (PLA's) is such that the cost is more aptly only dependent on gate quantity. The consequences of redefining cost for PLA's are studied with respect to covering algorithms. The major benefits are that a multipleoutput prime implicant (implicate) table can be viewed as a single output table and that minimal covers can be determined much more simply, especially for cyclic tables.
This paper describes an algorithm for minimizing an arbitrary Boolean function. The approach differs from most previous procedures in which first all prime implicants are found and then a minimal set is then determine...
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This paper describes an algorithm for minimizing an arbitrary Boolean function. The approach differs from most previous procedures in which first all prime implicants are found and then a minimal set is then determined. This procedure imposes a set of conditions on the selection of the next prime implicant in order to obtain a near minimal sum-of-products realization. Extension to the multipleoutput and incompletely specified function cases is given. An important characteristic of the proposed procedure is the relatively small amount of computer time spent to solve a problem, as compared to other procedures. The MINI algorithm may give better results for a large number of inputs and outputs if relatively few product terms are needed. This procedure is also well suited to find a solution for programmable logic arrays (PLA's) which internally implement large Boolean functions as a sum-of-products.
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