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A realization of multiple-output functions by a look-up table ring

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2004年第12期E87A卷 3141-3150页

作者： Qin, H Sasao, T Matsuura, M Nagayama, S Nakamura, K Iguchi, Y Kyushu Inst Technol Dept Elect & Comp Sci Iizuka Fukuoka 8208502 Japan Kyushu Inst Technol Ctr Microelect Syst Iizuka Fukuoka 8208502 Japan Meiji Univ Dept Comp Sci Kawasaki Kanagawa 2148571 Japan

A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 mum CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.

关键词： LUT cascade LUT ring multiple-output function reconfigurable logic programmable logic device

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Bi-partition of shared binary decision diagrams

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2002年第12期E85A卷 2693-2700页

作者： Matsuura, M Sasao, T Butler, JT Iguchi, Y Kyushu Inst Technol Dept Comp Sci & Elect Iizuka Fukuoka 8208502 Japan Meiji Univ Dept Comp Sci Kawasaki Kanagawa 2148571 Japan USN Postgrad Sch Dept Elect & Comp Engn Monterey CA 93943 USA Kyushu Inst Technol Dept Comp Sci & Elect Iizuka Fukuoka 8208502 Japan Kyushu Inst Technol Ctr Microelect Syst Iizuka Fukuoka 8208502 Japan

A shared binary decision diagram (SBDD) represents a multiple-output function, where nodes are shared among BDDs representing the various outputs. A partitioned SBDD consists of two or more SBDDs that share nodes. The separate SBDDs are optimized independently, often resulting in " reduction in the number of nodes over a single SBDD. We show " method for partitioning a single SBDD into two parts that reduces the node count. Among the benchmark functions tested, a node reduction of up to 23% is realized.

关键词： shared binary decision diagram SBDD bi-partition multiple-output function decomposition

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Compact SOP representations for multiple-output functions - An encoding method using multiple-valued logic

Compact SOP representations for multiple-output functions - ...

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31st IEEE International Symposium on multiple-Valued Logic (ISMVL 2001)

作者： Sasao, T Kyushu Inst Technol Dept Comp Sci & Elect Ctr Microelect Syst Iizuka Fukuoka 8208502 Japan

ISBN: (纸本)0769510833

This paper shows a method to represent a multiple-output function: Encoded characteristic function for non-zero poutputs (ECFN). The ECFN uses (n + u) binary variables to represent an n-input m-output function, where u = [log(2) m]. The size of the sum-of-products expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the optimal encoding produces SOPs with O(n) products, while the worst encoding produces SOPs with O(2(n)) products. We formulate encoding problem and show a heuristic optimization method. Experimental results using standard benchmark functions show the usefulness of the method.

关键词： multiple-output function encoding problem multiple-valued logic TDM SOP characteristic function

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Heuristics to minimize multiple-valued decision diagrams

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2000年第12期E83A卷 2498-2504页

作者： Babu, HMH Sasao, T Kyushu Inst Technol Dept Comp Sci & Elect Iizuka Fukuoka 8208502 Japan

In this paper, we propose a method to minimize multiple-valued decision diagrams (MDDs) for multiple-output functions. We consider the following: (1) a heuristic for encoding the 2-valued inputs;and (2) a heuristic for ordering the multiple-valued input variables based on sampling where each sample is a group of outputs. We first generate a 4-valued input 2-valued multiple-output function from the given 2-valued input 2-valued functions. Then we construct an MDD for each sample and find a good variable ordering. Finally, we generate a variable ordering from the orderings of MDDs representing the samples and minimize the entire MDDs. Experimental results show that the proposed method is much faster, and for many benchmark functions, it produces MDDs with fewer nodes than sifting. Especially, the proposed method generates much smaller MDDs in a short time for benchmark functions when several 2-valued input variables are grouped to form multiple-valued variables.

关键词： binary decision diagram (BDD) multiple-valued decision diagram (MDD) multiple-output function multiple-walled logic FPGA design

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Time-division multiplexing realizations of multiple-output functions based on shared multi-terminal multiple-valued decision diagrams

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1999年第5期E82D卷 925-932页

作者： Babu, H Sasao, T Kyushu Inst Technol Dept Comp Sci & Elect Iizuka Fukuoka 8208502 Japan

This paper considers methods to design multiple-output networks based on decision diagrams (DDs). TDM (time-division multiplexing) systems transmit several signals on a single line. These methods reduce: 1) hardware;2) logic levels;and 3) pins. In the TDM realizations, we consider three types of DDs: shared binary decision digrams (SBDDs), shared multiple-valued decision diagrams (SMDDs), and shared multiterminal multiple-valued decision diagrams (SMTMDDs). In the network, each non-terminal node of a DD is realized by a multiplexer (MUX). We propose heuristic algorithms to derive SMTMDDs from SBDDs. We compare the number of non-terminal nodes in SBDDs, SMDDs, and SMTMDDs. For nrm n, log n, and for many other benchmark functions, SMTMDD-based realizations are more economical than other ones, where nrm n is a (2n)-input (n + 1)-output function computing [root(X-2+Y-2) + 0.5],log n is an n-input n-output function computing [(2(n)-1)log(x+1)/nlog2], and /a/ denotes the largest integer not greater than a.

关键词： multiple-valued decision diagram (MDD) multiple valued logic multiple-output function time-division multiplexing (TDM)

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LOGIC DESIGN OF PROGRAMMABLE LOGIC-ARRAYS

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IEEE TRANSACTIONS ON COMPUTERS 1979年第9期28卷 609-617页

作者： KAMBAYASHI, Y KYOTO UNIV DEPT INFORMAT SCIKYOTO 606JAPAN

Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield. A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations. For such a function, reduction of the number of input is possible in many cases. Since the cost of a PLA is mainly determined by the number of pins and the chip, both of which are affected by the number of inputs, the reduction of the number of inputs is very important in PLA design. On the other hand, the reduction of the number of product terms in a sum-of-product expression is important in conventional random logic synthesis. Since there is a tradeoff problem between the number of inputs and the number of product terms, we give a design procedure by the following preference order: 1) minimizing the number of pins, 2) minimizing the number of product terms, 3) minimizing the number of circuits used in the PLA. These factors also determine the area required for a chip.

关键词： Incompletely specified logic function logic design multiple-output function programmable logic array reduction of the number of inputs two-level circuit

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