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Intelligent Online Configuration for DVFS multiprocessor architecture: Fuzzy Approach 32nd

Intelligent Online Configuration for DVFS Multiprocessor Arc...

32nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems (IEA/AIE)

作者： Yousra, Najar Ben Ahmed, Samir Univ Tunis El Manar High Inst Comp ISI Tunis Tunisia Univ Tunis El Manar Fac Sci Math Phys & Nat FST Tunis Tunisia

ISBN: (纸本)9783030229993;9783030229986

The use of fuzzy logic to generate optimal actions for hardware architecture reconfiguration offers flexible and efficient solutions. In this paper, a new fuzzy approach is proposed in order to guarantee the balance between real time periodic application schedulability and energy consumption optimization under multi-core architecture. Dynamic voltage/frequency scaling (DVFS) has been a key technique in exploiting the processors configurable characteristics. However, for large class of applications in embedded real time systems, the variable operating frequency interferes with tasks deadline respect. The problem is seen as multi-criteria multi-objective decision making issue with dependent criteria. The approach calculates, in offline mode and in online mode, the optimal number of activated homogenous cores and their frequency. Simulated and tested on periodic task sets generated with different system charges, the proposed intelligent technique is support decision system that shows significant results.

关键词： Fuzzy Decision Making (FDM) Dynamic Voltage/Frequency Scaling (DVFS) CPU energy consumption Periodic real time application multiprocessor architecture Schedulability

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Fuzzy Decision Efficiency for multiprocessor architecture Configuration 23rd

Fuzzy Decision Efficiency for Multiprocessor Architecture Co...

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23rd KES International Conference on Knowledge-Based and Intelligent Information and Engineering Systems (KES)

作者： Yousra, Najar Samir, Ben Ahmed Univ Tunis el Manar High Inst Comp ISI Tunis Tunisia Univ Tunis el Manar Fac Sci Math Phys & Nat Tunis Tunisia

Dynamic voltage/frequency scaling (DVFS) has been an efficient technique in exploiting multi-processors configurable characteristics. However, for large class of embedded real time applications, changing processors frequency interferes with tasks deadline guarantee. Under homogenous multiprocessor architecture, we are interested in intelligent offline/online reconfiguration based on fuzzy inference system. This paper investigates the efficiency of using fuzzy decision in multiprocessor architecture configuration. Goals of decision making are system schedulability guarantee and energy consumption optimization. Experiments concern real time periodic tasks scheduled with global EDF and realized over a developed simulation environment that supports DVFS technique. Different simulations were realized on H264 Video Decoder in order to evaluate the proposed approach response. (C) 2019 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (https://***/licenses/by-nc-nd/4.0/) Peer-review under responsibility of KES International.

关键词： Fuzzy decisions DVFS Energy Optimisation schedulability multiprocessor architecture

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Fuzzy Decision Efficiency for multiprocessor architecture Configuration

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Procedia Computer Science 2019年 159卷 301-312页

作者： Najar Yousra Ben Ahmed Samir University of Tunis el Manar High Institute of computing (ISI) Tunisia University of Tunis el Manar Faculty of Science Mathematics Physics and Natural Tunisia

关键词： Fuzzy decisions DVFS Energy Optimisation schedulability multiprocessor architecture

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Effective Information Retrieval Algorithm for Linear multiprocessor architecture 1

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50th Annual Convention of the Computer-Society-of-India (CSI) on Digital Life

作者： Khan, Zaki Ahmad Siddiqui, Jamshed Samad, Abdus Aligarh Muslim Univ Dept Comp Sci Fac Sci Aligarh 202002 Uttar Pradesh India Aligarh Muslim Univ Univ Womens Polytech Aligarh 202002 Uttar Pradesh India

ISBN: (数字)9789811085338

ISBN: (纸本)9789811085338;9789811085321

Information retrieval is magnetizing important interest due to exponential development of the quantity of information accessible in different formats such as textual, numeric and image formats. A number of applications can be downloaded in parallel by several servers available on net using downloading applications. These applications may vary depending upon the mechanism used to improve to downloading time. One of the methods to speedup downloading is to incorporate concurrency. In this paper, a new approach for downloading files is proposed that uses a parallel architecture as a server. The server named as Linear-Crossed Cube (LCQ) is based on linear topology with all desirable topological properties. The load on the server balances dynamically. The proposed downloading algorithm is implemented, and downloading time is evaluated for number of queries. A comparative simulation study has been carried out along with the execution time to download file. The simulation results show significant improvement in the downloading time by using the proposed system.

关键词： Information retrieval multiprocessor architecture Server Download Load balancing

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Realizing multioperations and multiprefixes in Thick Control Flow processors

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MICROPROCESSORS AND MICROSYSTEMS 2023年 98卷

作者： Forsell, Martti Roivainen, Jussi Leppanen, Ville Traeff, Jesper Larsson VTT Espoo Finland Univ Turku Fac Technol Turku Finland Vienna Univ Technol Fac Informat TU Wien Vienna Austria

Multioperations are primitives of parallel computation by which threads perform reductions, e.g., additions, on values provided by multiple threads into a single value in a constant number of steps. Multiprefixes resemble multioperations, but return to each participating thread a cumulative ordered reduction of all preceding values. Algorithmically, multioperations and multiprefixes can speed up parallel programs by a logarithmic factor over their single operation counterparts. In this paper, we introduce architectural techniques for realizing multioperations and multiprefixes in so-called Thick Control Flow (TCF) processors. A thick control flow is a computational construct that bundles homogeneous threads following the same control path into a data parallel entity. Our proposed processors optimized for executing TCFs feature a frontend-backend structure with low-latency processing of TCF-common computations and high-throughput execution of data parallel parts. Our solution relies on step caches and equally sized multioperation scratchpads, while on the memory side, we make use of active memory modules. The idea is to compute partial results in backend units to reduce the traffic to the referred shared memory location. The final multioperation result is then computed in the active memory unit of the target memory module. Multiprefixes use an additional phase where the final results are computed with a help of backend-wise prefixes. According to our evaluation, the proposed techniques indeed speed up certain N data element algorithms by a log N factor with reasonable hardware costs.

关键词： Parallel computing multiprocessor architecture Thick Control Flow Multioperation Multiprefix

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SAC-tool: a tool for scheduling analysis and correction of multiprocessor Real Time Systems 15

SAC-tool: a tool for scheduling analysis and correction of m...

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15th IEEE/ACS International Conference on Computer Systems and Applications (AICCSA)

作者： Faten, Mrabet Walid, Karamti Adel, Mahfoudhi Univ Sfax Dept Comp Sci Fac Econ & Management Sfax Tunisia Higher Inst Comp Sci & Math Dept Comp Sci Monastir Tunisia Taif Univ Dept Informat Technol Coll Comp & Informat Technol At Taif Saudi Arabia

ISBN: (纸本)9781538691205

For several years, real time systems (RTS) have been continuously growing and complex. The time needed for their development is consequently very important and their accuracy is crucial for human and economic disaster prevention. In this vein, scheduling analysis and correction at the early stage of RTS application life cycle can effectively reduce potential scheduling faults (temporal faults). Thus, reduce the important cost, risk and effort of development. However, despite the diversity of scheduling analysis techniques, they can only detect the schedulability of an RTS without the proposal of possible correction, if the system is detected non-schedulable. Existing scheduling analysis techniques lack autonomy, so require other rigorous means (tools) to assist them in correction. It is then recommended to integrate into scheduling analysis techniques a method for correction to ensure autonomy and to save time and effort. In this paper we present a prototype of the SAC-tool (Scheduling analysis and correction tool) implementing a new method of scheduling analysis and correction dedicated for multiprocessor RTS. To illustrate and extend this method a static view via UML class diagram is presented in this paper. Two main steps are provided in SAC-tool, a configuration editing step and a scheduling analysis and correction step.

关键词： Real-Time Systems multiprocessor architecture scheduling analysis scheduling correction partitionning assignment tasks migration SAC-tool

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A Novel Task-to-Processor Assignment Approach for Optimal multiprocessor Real-Time Scheduling

A Novel Task-to-Processor Assignment Approach for Optimal Mu...

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Duy Doan Kiyofumi Tanaka School of Information Science Japan Advanced Institute of Science and Technology Nomi Ishikawa Japan

ISBN: (纸本)9781538666906

Recent decades have recognized the popularization of multiprocessor architectures in real-time embedded systems. Real-time task scheduling in such systems has become a challenging problem as a result. In this paper, we are presenting an optimal scheduling algorithm, which can successfully schedule any task sets with no deadline miss if the total utilization of tasks does not exceed the capacity of the involved system. The proposed algorithm called LLA introduces a so-called fixed task-scheduling plan for every time interval that is defined as the time period between two consecutive job releases. At the beginning of each interval, LAA makes the scheduling plan by predicting tasks' requested amount of execution time within the interval and then arranging these amounts to processors appropriately respecting to requirements of scheduling. By this approach, LAA can extremely reduce the number of scheduler invocations to the number of job releases. Furthermore, simulation results show that our algorithm has lower time complexity while retaining the schedulability, task preemption, and task migration competitive to the existing optimal scheduling algorithms.

关键词： Real-time operating system Scheduling algorithm multiprocessor Runtime overhead multiprocessor real time operating system Scheduling algorithms multiprocessor architecture time schedule Simulation results Time intervals TASK SCHEDULING Optimal scheduling jobs Religious Missions execution time complexity classes

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Operating System Support to an Online Hardware-Software Co-Design Scheduler for Heterogeneous Multicore architectures 20

Operating System Support to an Online Hardware-Software Co-D...

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20th IEEE International Conference on Embedded and Real- Time Computing Systems and Applications (RTCSA 2014).

作者： Bueno, Maikon A. F. de Holanda, Jose A. M. Pereira, Erinaldo Marques, Eduardo Univ Sao Paulo Inst Math & Comp Sci Sao Carlos SP Brazil

ISBN: (纸本)9781479939541

This paper aims at designing and implementing a scheduler model for heterogeneous multiprocessor architectures based on software and hardware. As a proof of concept, the scheduler model was applied to the Linux operating system running on the SPARe Leon3 processor. In this sense, performance monitors have been implemented within the processors, which identify demands of processes in real-time. For each process, its demand is projected for the other processors in the architecture and then, it is performed a balancing to maximize the total system performance by distributing processes among processors. The Hungarian maximization algorithm, used in balancing scheduler was developed in hardware, and provides greater parallelism and performance in the execution of the algorithm. The scheduler has been validated through the parallel execution of several benchmarks, resulting in decreased execution times compared to the scheduler without the heterogeneity support.

关键词： Benchmark testing Integrated circuits Monitoring Benchmark testing scheduler program PROCESSOR multiprocessor architecture Computer hardware System performance Integrated circuits Electronic circuits architecture Support Systems parallel execution Legal Executions Co-design Operating systems

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HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms

HNCP-II: A 16-core 65nm microprocessor ASIC for image proces...

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9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

作者： Boussadi, Mohamed Amine Tixier, Thierry Landrault, Alexis Derutin, Jean-Pierre Inst Pascal UMR 6602 CNRS UBP IFMA F-63171 Aubiere France

ISBN: (纸本)9781479958108

In many video and image processing applications, complexity has reached a point where the performance requirements can no longer be supported by standard architectures based on a single processor. This is why many systems are based on multiprocessor architecture. In this paper, we present HNCP-II a 16-core flexible distributed memory ASIC dedicated to embedded application field (image processing applications). Connected through a torus on-chip network, each tile of the overall system includes an open-source RISC processor, a floating point unit, a video management module and a set of built in hardware features for multicore communication. This specific hardware enables to meet most relevant overall parallelism scheme (parallel skeletons) thanks to software-configurable modules. Results are presented for two image processing algorithms in term of execution time, speedup and efficiency. Area, power and timing performance of the synthesized ASIC are given for a CMOS 65nm technology node.

关键词： image processing algorithm network-on-chip application specific integrated circuits ASIC Uniprocessor Tile toruses macroprocessor multiprocessor architecture

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Supervised Sharing of Virtual Channels In Networks-on-Chip

Supervised Sharing of Virtual Channels In Networks-on-Chip

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9th IEEE International Symposium on Industrial Embedded Systems (SIES)

作者： Kostrzewa, Adam Tobuschat, Sebastian Axer, Phillip Ernst, Rolf Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Network Engn Braunschweig Germany

ISBN: (纸本)9781479940226

Networks-on-Chip (NoCs) for embedded multiprocessor architectures require special mechanisms for sharing resources such as links and queues in network routers. A widely used solution is virtual-channel flow control which prevents head-of-line blocking and isolates different data streams. However, the number of virtual channels (VCs) is limited by the available buffer space in the routers. Due to the evergrowing number of applications and mutual exclusive requirements it may not be possible to assign each application a unique VC. In this paper we present a Resource Broker (RB) which is an overarching mechanism that schedules NoC traffic. It allows predictable and efficient sharing of VCs without compromising isolation and Quality-of-Service guarantees. We show that by managing the NoC traffic with the RB, we drastically reduce blocking and improve the overall utilization and hence the system performance.

关键词： Artificial neural networks virtual channels Artificial neural networks buffer space multiprocessor architecture Rubidium Resource sharing Queue Network System performance

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