We present a scalable framework for real-time data-intensive systems on commodity multiprocessor workstations. The framework is an extension of the process network model, which captures parallelism, guarantees determi...
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We present a scalable framework for real-time data-intensive systems on commodity multiprocessor workstations. The framework is an extension of the process network model, which captures parallelism, guarantees determinate execution, and executes in bounded memory. We implement the framework using lightweight POSIX threads and prototype a 4-GFLOP sonar beamformer on a 12-processor 336-MHz Sun Enterprise server. The beamformer scales nearly linearly from 1 to 12 processors.
Future and current high-performance computing applications will have to change and adapt as node architectures evolve. The application of advanced architecture simulators will play a crucial role for the design and op...
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Future and current high-performance computing applications will have to change and adapt as node architectures evolve. The application of advanced architecture simulators will play a crucial role for the design and optimization of future data intensive applications. In this paper, we present our simulation-based framework for analyzing the scalability and performance of a number of critical optimizations of a massively parallel genomic search application, mpiBLAST, using an advanced macroscale simulator (SST/macro). We report the use of our framework for the evaluation of three potential improvements of mpiBLAST: 1) enabling high-performance parallel output;2) an approach for caching database fragments in memory;and 3) a methodology for pre-distributing database segments. In our experimental setup, we performed query sequence matching on the genome of the yellow fever mosquito, Aedes aegypti.
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities...
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ISBN:
(纸本)9781509032198
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper applies the MapReduce parallel programming model to embedded multi-processor system-on-chip (MPSoC). We implement the proposed MPSoC in system-level SystemC and evaluate its performance using commercial ESL tools. Experimental results show that the proposed MPSoC can achieve up to 2.1x performance improvement compared with Phoenix on general-purpose embedded platform.
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities...
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With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper presents a MapReduce-based multiprocessor system-on-chip (MPSoC) for providing efficient architectural supports to MapReduce parallel programming paradigm. We implement the proposed MPSoC in cycle-accurate SystemC and evaluate its performance using a set of representative MapReduce applications. Results show that the proposed MPSoC can achieve up to 2.1x overall performance improvement over the current general purpose multicore processors in typical MapReduce applications. Keywords: multiprocessor system-on-chip, MapReduce, multiprocessor programming, embedded systems
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities...
详细信息
ISBN:
(纸本)9781509032204
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper applies the MapReduce parallel programming model to embedded multi-processor system-on-chip (MPSoC). We implement the proposed MPSoC in system-level SystemC and evaluate its performance using commercial ESL tools. Experimental results show that the proposed MPSoC can achieve up to 2.1× performance improvement compared with Phoenix on general-purpose embedded platform.
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