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CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 2006年第6期153卷 539-544页

作者： Ray, K. C. Dhar, A. S. Indian Inst Technol Dept E&ECE Kharagpur 721302 W Bengal India

Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 mu m CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm(2) (approximately).

关键词： signal processing CUSPED GEOMETRIES operating frequency sidelobe window function ARCHITECTURE real-time application program Digital arithmetic Building construction Spectral leakage CMOS technology Frequency analysis multiprogramming Spectrum Analysis first-in first-out

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ALGORITHMS IMPLEMENTING DISTRIBUTED SHARED MEMORY

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COMPUTER 1990年第5期23卷 54-64页

作者： STUMM, M ZHOU, SN UNIV TORONTO DEPT COMP SCITORONTO M5S 1A4ONTARIOCANADA

Four basic algorithms for implementing distributed shared memory are compared. Conceptually, these algorithms extend local virtual address spaces to span multiple hosts connected by a local area network, and some of them can easily be integrated with the hosts' virtual memory systems. The merits of distributed shared memory and the assumptions made with respect to the environment in which the shared memory algorithms are executed are described. The algorithms are then described, and a comparative analysis of their performance in relation to application-level access behavior is presented. It is shown that the correct choice of algorithm is determined largely by the memory access behavior of the applications. Two particularly interesting extensions of the basic algorithms are described, and some limitations of distributed shared memory are noted

关键词： application-level access behavior distributed shared memory environment local area network local area networks local virtual address spaces memory access behavior multiple hosts multiprogramming network operating systems performance shared memory algorithms virtual memory systems

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Efficient processor management schemes for mesh-connected multicomputers

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PARALLEL COMPUTING 2001年第8期27卷 1057-1078页

作者： Yoo, BS Das, CR Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

This paper investigates various processor management techniques for improving the performance of mesh-connected multicomputers. Unlike almost all prior work where the focus was on improving the submesh recognition ability of the processor allocation algorithms, this research examines other alternatives to improve system performance beyond what is achievable with usually assumed first come first served (FCFS) scheduling and any allocation. First, we use the smallest job first (SJF) policy to improve the spatial parallelism in a mesh. Next. we introduce a generic processor management scheme called multitasking and multiprogramming (M(2)). Then, an M(2) policy for mesh-connected multicomputers called virtual mesh (VM) is proposed and analyzed. The proposed VM scheme allows multiprogramming of jobs on several VMs. Finally, a novel approach called limit allocation is used for job allocation. With this scheme, a job (submesh) size is reduced if the job cannot be allocated. The objective here is to reduce the job waiting time and hence improve the overall performance. While all of the three approaches are viable alternatives to reduce the average job response time under various workloads, the VM and the limit allocation techniques are especially attractive for providing some additional features. The VM scheme brings in the concept of time-sharing execution for better efficiency and limit allocation shows how job size restriction can be beneficial for performance and fault-tolerance in a mesh topology. Moreover, the limit allocation scheme using even the simplest allocation policy can outperform any other approach. (C) 2001 Published by Elsevier Science B.V.

关键词： first fit limit allocation multiprogramming performance study resource management smallest job first

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Application of signal-processing techniques to dipole excitations in the finite-difference time-domain method

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JOURNAL OF ELECTROMAGNETIC WAVES AND APPLICATIONS 2002年第5期16卷 671-687页

作者： Oguz, U Gürel, L Bilkent Univ Dept Elect & Elect Engn TR-06533 Ankara Turkey

The applications of discrete-time signal-processing techniques, such as windowing and filtering for the purpose of implementing accurate excitation schemes in the finite-difference time-domain (FDTD) method are demonstrated. The effects of smoothing windows of various lengths and digital lowpass filters of various bandwidths and characteristics are investigated on finite-source excitations of the FDTD computational domain. Both single-frequency sinusoidal signals and multifrequency arbitrary signals are considered.

关键词： Bandwidth Low pass filters TimeDif Excitation signal processing multiprogramming Filtration dipoles Finite difference time domain method smoothing

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Virtual network transport protocols for Myrinet

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IEEE MICRO 1998年第1期18卷 53-63页

作者： Chun, BN Mainwaring, AM Culler, DE Univ Calif Berkeley Div Comp Sci Berkeley CA 94720 USA

This article describes a protocol for a general-purpose cluster communication system that supports multiprogramming with virtual networks, direct and protected network access, reliable message delivery using message time-outs and retransmissions, a powerful return-to-send error model for applications, and automatic network mapping. The protocols use simple, low-cost mechanisms that exploit properties of our interconnect without limiting flexibility, usability, or robustness. We have implemented the protocols in an active message communication system that runs a network of 100+ Sun UltraSPARC workstations interconnected with 40 Myrinet switches. A progression of microbenchmarks demonstrate good performance - 42 microsecond round-trip times and 31 MB/s node-to-node bandwidth - as well as scalability under heavy load and graceful performance degradation in the presence of high contention.

关键词： Network Transport Protocols Myrinet LAN Cluster Communications multiprogramming

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SCHEDULING PREEMPTIVE MULTIPROCESSOR TASKS ON DEDICATED PROCESSORS

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PERFORMANCE EVALUATION 1994年第4期20卷 361-371页

作者： BIANCO, L BLAZEWICZ, J DELLOLMO, P DROZDOWSKI, M POLITECHN POZNANSKA INST INFORMATPOZNANPOLAND CNR IST ANAL SIST & INFORMATROMEITALY

In the classical scheduling theory it is widely assumed that any task requires for its processing only one processor at a time. In this paper the problem of deterministic scheduling of tasks requiring for their processing more than one processor at a time, i.e., a constant set of dedicated processors, is analyzed. Schedule length is assumed to be a performance measure. Tasks are assumed to be preemptable and independent. Low order polynomial algorithms for simple cases of the problem are given. Then a method to solve the general version of the problem for a limited number of processors is presented, while the case of an arbitrary number of processors is known to be NP-hard. Finally, a version of the problem, where besides processors every task can also require additional resources, is considered.

关键词： multiprogramming

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Dynamically adapting to system load and program behavior in multiprogrammed multiprocessor systems

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2002年第12期14卷 957-985页

作者： Kazi, IH Lilja, DJ Sun Microsyst Inc Palo Alto CA 94303 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

Parallel execution of application programs on a multiprocessor system may lead to performance degradation if the workload of a parallel region is not large enough to amortize the overheads associated with the parallel execution. Furthermore, if too many processes are running on the system in a multiprogrammed environment, the performance of the parallel application may degrade due to resource contention. This work proposes a comprehensive dynamic processor allocation scheme that takes both program behavior and system load into consideration when dynamically allocating processors. This mechanism was implemented on the Solaris operating system to dynamically control the execution of parallel C and Java application programs. Performance results show the effectiveness of this scheme in dynamically adapting to the current execution environment and program behavior, and that it outperforms a conventional time-shared system. Copyright (C) 2002 John Wiley Sons, Ltd.

关键词： processor allocation dynamic adaption loop-level parallelism shared memory multiprocessor system multiprogramming

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Evaluation and performance analysis of the process cache: a partitioned multi-process secondary cache

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COMPUTERS & ELECTRICAL ENGINEERING 1998年第3-4期24卷 201-221页

作者： Gaede, RK Golos, F McMahan, MD Kulick, JH Univ Alabama Dept Elect & Comp Engn Huntsville AL 35899 USA

This paper describes an advance in multiprocess cache system design called the process cache in which the secondary cache has segments dedicated to each process. This approach is in contrast to a monolithic secondary cache in which every process' data can be distributed throughout the secondary cache. The process cache system is equally applicable to instruction and data caches, however, its performance is evaluated only for an instruction cache in this paper. The goal of the process cache architecture is to improve program performance in environments which have high context switch rates and long tertiary memory access times. This paper presents an instruction only trace-driven simulation that demonstrates that for long tertiary memory latencies (10 mu s) and short context switch intervals (1 ms) the process cache architecture significantly (11-14%) outperforms monolithic secondary cache architectures independent of cache memory size, associativity, or cache line size. This improvement does not require significantly more hardware than current cache memory designs. Additionally, we present an architecture which allows the system to allocate different amounts of secondary cache memory per process. Furthermore, process caches provide a high degree of locality for process information in a multiple processor configuration allowing efficient task migration between processors. (C) 1998 Elsevier Science Ltd. All rights reserved.

关键词： cache memories performance analysis multiprogramming

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PASCAL, MODULA-2 AND MULTI-TASKING KERNEL IMPLEMENTATION

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SOFTWARE ENGINEERING JOURNAL 1987年第6期2卷 205-212页

作者： AYANDEH, S MORRIS, EL UNIV EXETER DEPT ENGN SCIEXETER EX4 4QFDEVONENGLAND UNIV WESTERN ONTARIO FAC ENGN SCILONDON N6A 5B9ONTARIOCANADA

This paper presents a comparison of Pascal and Modula-2 based on the implementation of the basic components of a multi-tasking kernel. The major issues involved in high-level language implementation of a stand-alone multi-tasking kernel on a microprocessor system are the transportation of the language support system and what may be termed software engineering considerations. The merits of Pascal and Modula-2 with respect to these issues are compared. Standard Pascal is a sequential language, and the development of the multi-tasking features of the kernal has to take place outside the scope of the language. The Modula-2 language (nucleus), however, allows the kernal to be built entirely using high-level constructs. Issues of language run-time support and portability are also covered. These topics and the high-level handling of interrupts have received little attention in the literature on Modula-2. The Modula-2 kernel also provides a possible implementation of the ‘MODULE processes’.

关键词： software engineering Operating systems language run-time support multiprogramming Pascal multi-tasking kernel high-level language sequential language portability High level languages Modula interrupts Modula-2 microprocessor system

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PERFORMANCE EVALUATION OF CENTRALIZED DATABASES WITH STATIC LOCKING

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1985年第4期11卷 346-355页

作者： THOMASIAN, A Hawthorne Res. Lab. IBM Thomas J. Watson Res. Cent. Yorktown Heights NY 10598 USA

The performance of transaction processing systems is determined by the contention for hardware as well as software resources (database locks), due to the concurrency control mechanism of the database being accessed by transactions. The author considers a transaction processing system with a set of dominant transaction classes. Each class needs to acquire a certain subset of the locks in the database before it can be processed, i.e., predeclared lock requests with static locking. Straightforward application of the decomposition method requires the numerical solution of a two-dimensional Markov chain. Equivalently, a hierarchical simulation method, where the computer system is represented by a composite queue with exponential service rates, can be used to analyze the system.

关键词： Two Phase Locking Approximate Solution Concurrency Control Decomposition Hierarchical Simulation Markov Chain multiprogramming Queueing Network Model Queueing Systems With Multiple Contention Points Static Locking

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