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A Model of SIMD Machines and a Comparison of Various Interconnection networks

IEEE Transactions on Computers 1979年第12期C-28卷 907-917页

作者： Siegel, Howard Jay School of Electrical Engineering Purdue University West Lafayette IN 47907 United States

A formal mathematical model of single instruction stream-multiple data stream (SIMD) machines is defined. It is used as a basis for analyzing various types of interconnection networks that have been discussed in the literature. The networks are evaluated in terms of the lower and upper bounds on the time required for each of the networks discussed to simulate the other networks. SIMD machine algorithms are presented as proofs of the upper time bounds on these simulation tasks. These simulations are used to demonstrate techniques for proving the correctness of SIMD machine algorithms, i.e., analyzing the simultaneous flow of n data items among n processors. Processor address masks, a concise notation for activating and deactivating processors, are used in the algorithms. The methods used to prove the lower bounds and to construct (and prove correct) simulation algorithms to show the upper bounds can be generalized and applied to the analysis of other networks. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

关键词： array processors computer architecture Illiac IV Index Terms-Algorithm correctness interconnection networks n-cube array parallel processing perfect shuffle permutation networks SIMD machines STARAn

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The Indirect Binary n-cube Microprocessor array

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IEEE Transactions on Computers 1977年第5期C-26卷 458-473页

作者： Pease, Marshall C. Information Science Laboratory Information Science and Engineering Division Stanford Research Institute Menlo Park CA 94025 United States

This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor we mean a processor realized on one or a few semiconductor chips that include arithmetic and logical facilities and some memory. The current state of LSI technology makes this approach a feasible and attractive candidate for use in a macrocomputer facility. The array studied is called the indirect binary n-cube array. It uses a network of switching nodes to obtain a high degree of flexibility of the connections among the microprocessors without placing excessive demands on the scarce resource of the pins on a microprocessor. A number of computational procedures are discussed. Detailed attention is given to the communication requirements for algorithms used in the solution of partial differential equations in two or three dimensions. The use of the array for the radix-2 fast Fourier transform (FFT) and related signal processing applications is considered. Its use for matrix operations is also discussed, with particular attention given to matrix multiplication as the most basic operation. The final conclusion is that the indirect binary n-cube array is useful for a very wide range of important problems, and thus is an attractive candidate for the design of a large-scale array of microprocessors. Copyright © 1977 by The Institute of Electrical and Electronics Engineers, Inc.

关键词： Admissible maps array processor fast Fourier transform grid computations microprocessor array n-cube array parallel matrix multiplication parallel processing permutation network switching network triangular permutations virtual array

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