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near-data processing: INSIGHTS FROM A MICRO-46 WORKSHOP

IEEE MICRO 2014年第4期34卷 36-42页

作者： Balasubramonian, Rajeev Chang, Jichuan Manning, Troy Moreno, Jaime H. Murphy, Richard Nair, Ravi Swanson, Steven Univ Utah Salt Lake City UT 84112 USA Google Menlo Pk CA USA Micron Boise ID USA IBM Thomas J Watson Res Ctr New York NY USA Univ Calif San Diego San Diego CA 92103 USA

AFTER A DECADE-LONG DORMANCY, INTEREST IN near-data processing (NDP) HAS SPIKED. A WORKSHOP ON NDP WAS ORGANIZED AT MICRO-46 AND WAS WELL ATTENDED. GIVEN THE INTEREST, THE ORGANIZERS AND KEYNOTE SPEAKERS HAVE ATTEMPTED TO CAPTURE THE KEY INSIGHTS FROM THE WORKSHOP FOR WIDER DISSEMINATION. THIS ARTICLE DESCRIBES WHY NDP IS COMPELLING TODAY AND IDENTIFIES UPCOMING CHALLENGES IN REALIZING ITS POTENTIAL.

关键词： Bandwidth allocation big data Computational modeling Computer architecture Costs data movement Distributed databases History history of computing near-data processing

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near-data processing

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IEEE MICRO 2016年第1期36卷 4-5页

作者： Balasubramonian, Rajeev Grot, Boris Univ Utah Salt Lake City UT 84112 USA Univ Edinburgh Sch Informat Edinburgh EH8 9YL Midlothian Scotland

The guest editors introduce the two theme articles and the invited position papers in the issue. [ABSTRACT FROM PUBLISHER]

关键词： Big data data processing efficiency Multiprocessors near-data processing nonvolatile memory Parallel processing performance Random access memory Special issues and sections

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near-data processing-Enabled and Time-Aware Compaction Optimization for LSM-tree-based Key-Value Stores 19

Near-Data Processing-Enabled and Time-Aware Compaction Optim...

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48th International Conference on Parallel processing (ICPP)

作者： Sun, Hui Liu, Wei Huang, Jianzhong Fu, Song Qiao, Zhi Shi, Weisong Anhui Univ Hefei Anhui Peoples R China Huazhong Univ Sci & Technol Wuhan Hubei Peoples R China Univ North Texas Denton TX USA Wayne State Univ Detroit MI USA

ISBN: (纸本)9781450362955

With the growing volume of storage systems, the traditional relational databases cannot reach the high performance required by big-data applications. As high-throughput alternatives to relational databases, LSM-tree-based key-value stores (KV stores in short) are confronted with degraded write performance during compaction under update-intensive workloads. To address this issue, we design and implement a time-aware compaction optimization framework for KV stores called TStore. TStore explores the near-data processing (i.e., NDP) model. It dynamically partitions compaction tasks into both host and NDP-enabled device to minimize the total time of compaction. The partitioned compaction tasks are conducted by the host and the device in parallel. The NDP-based devices exhibit low-latency, high-performance and high-bandwidth capability, thus facilitating key-value stores. TStore can not only accomplish compaction for KV stores, but also improve overall performance by removing bottleneck in compaction. Results show that the TStore with an NDP framework can achieve 3.8x and 1.9x performance improvement over LevelDB and Co-KV under the db_bench workload. In addition, the TStore-enabled KV store outperforms LevelDB and Co-KV by a factor of 3.6x and 1.9x in throughput and 72.0% and 48.9% in latency, respectively, under realistic workloads generated by YCSB.

关键词： near-data processing LSM-tree Key-Value Store Compaction Time-Aware Offloading and Partitioning

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near-data processing for dynamic graph analytics

Near-data processing for dynamic graph analytics

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作者： Hein, Eric Robert Georgia Institute of Technology

学位级别：博士

Massive data rates in cybersecurity, simulation, and social media analysis applications are driving rapid advances in the field of streaming graph analytics. The data structures that enable streaming graph analytics pose unique challenges for high-performance computing system designers. When the sorted, contiguous arrays of static graphs are replaced with the fragmented, linked data structures of dynamic graphs, these systems struggle to reach the memory bandwidth saturation point. Behaviors such as pointer-chasing and poor spatial locality expose the true latency of modern memory devices, which has not kept up with processor clock rates. This dissertation develops a streaming graph benchmark, DynoGraph, which is distinguished from static graph benchmarks by the use of realistic streaming graph inputs and dynamic graph data structures. The benchmark is used to expose performance pitfalls in existing implementations. These insights flow into the design of near-memory accelerators for streaming graph analytics, as well as software improvements. The Emu architecture is identified as a promising solution for accelerating algorithms with low spatial locality, unbalanced parallelism, and fine-grained memory accesses, since it is able to maintain high memory bandwidth utilization in a worst-case pointer-chasing scenario. The work culminates in a characterization of the Emu Chick hardware prototype, proposing efficient programming primitives, highlighting necessary system improvements, and demonstrating the potential for greatly improved performance on this important class of workloads.

关键词： Computer architecture Streaming graph analytics Graph algorithms High-performance computing near-data processing

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On the necessity of explicit cross-layer data formats in near-data processing systems

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DISTRIBUTED AND PARALLEL dataBASES 2022年第1期40卷 27-45页

作者： Weber, Lukas Vincon, Tobias Knoedler, Christian Solis-Vasquez, Leonardo Bernhardt, Arthur Petrov, Ilia Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Hsch Str 10 D-64289 Darmstadt Germany Reutlingen Univ DBLab Alteburgerstr 150 D-72762 Reutlingen Germany

Massive data transfers in modern data-intensive systems resulting from low data-locality and data-to-code system design hurt their performance and scalability. near-data processing (NDP) and a shift to code-to-data designs may represent a viable solution as packaging combinations of storage and compute elements on the same device has become feasible. The shift towards NDP system architectures calls for revision of established principles. ions such as data formats and layouts typically spread multiple layers in traditional DBMS, the way they are processed is encapsulated within these layers of abstraction. The NDP-style processing requires an explicit definition of cross-layer data formats and accessors to ensure in-situ executions optimally utilizing the properties of the underlying NDP storage and compute elements. In this paper, we make the case for such data format definitions and investigate the performance benefits under RocksDB and the COSMOS hardware platform.

关键词： near-data processing data format data layout FPGA

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Non-Invasive, Memory Access-Triggered near-data processing for DNN Training Acceleration on GPUs

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IEEE ACCESS 2024年 12卷 142651-142667页

作者： Ham, Hyungkyu Cho, Hyunuk Kim, Minjae Park, Jueon Hong, Jeongmin Sung, Hyojin Park, Eunhyeok Lim, Euicheol Kim, Gwangsun POSTECH Dept Comp Sci & Engn Pohang 37673 South Korea Seoul Natl Univ Dept Comp Sci & Engn Seoul 08826 South Korea Rebellions Inc Seongnam 13556 South Korea Seoul Natl Univ Grad Sch Data Sci Seoul 08826 South Korea SK Hynix Incheon 17336 South Korea

Currently, GPUs face significant challenges due to limited off-chip bandwidth (BW) and memory capacity during DNN training. To address these bottlenecks, we propose a memory access-triggered near-data processing matNDP architecture that offloads memory- and communication-bound operations. With mat NDP, normal memory accesses also serve as implicit NDP requests to enable NDP in anon-invasive manner without modifying core-side ISA/microarchitecture/SW, for practicality. Additionally, mat NDP enables on-the-fly NDP where the data already supplied in normal memory requests for compute-bound operations are also used for NDP;thus, mat NDP can overlap even dependent kernels while also reducing memory traffic. Moreover, with the overlap, memory bandwidth (BW) underutilized by GPU cores can be used by NDP units to improve performance under the same total memory BW. The mat NDP units can be deployed to heterogeneous memory devices in a system. First, we deploy them near GPU's memory controllers. Secondly, our NDP units are deployed in memory expanders connected to multiple GPUs to create an NDP-enabled memory eXpander Network (NDPXNet). . It can entirely offload gradient reduction and optimizer in data-parallel training, achieving additional speedups while eliminating redundancy in memory usage and optimizer execution. Thus, we 1) enable NDP without core HW/SW changes, 2) overlap the execution of dependent layers, and 3) offload both memory- and communication-bound operations from GPUs in DNN training. Through our deep learning compiler support, NDP kernels can be generated automatically without any model code modification. Consequently, mat NDP can improve training throughput by up to 2.73x x and reduce energy by up to 41.4%.

关键词： near-data processing deep neural networks deep neural networks GPU GPU memory expansion memory expansion memory expansion

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Asynchronous Compaction Acceleration Scheme for near-data processing-enabled LSM-tree-based KV Stores

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2024年第6期23卷 1-33页

作者： Sun, Hui Lou, Bendong Zhang, Chaowei Zhao, Chao Kong, Deyan Yue, Yinliang Huang, Jianzhong Qin, Xiao Anhui Univ 111 Jiulong Rd Hefei 230601 Anhui Peoples R China 88 South Daxue Rd Yangzhou 225127 Jiangsu Peoples R China Huazhong Univ Sci & Technol 1037 Luoyu Rd Wuhan Hubei Peoples R China Zhongguancun Lab Cuihu North Rd 2 Beijing Peoples R China Auburn Univ Auburn AL USA

LSM-tree-based key-value stores (KV stores) convert random-write requests to sequence-write ones to achieve high I/O performance. Meanwhile, compaction operations in KV stores update SSTables in forms of reorganizing low-level data components to high-level ones, thereby guaranteeing an orderly data layout in each component. Repeated writes caused by compaction (a.k.a. write amplification) impacts I/O bandwidth and overall system performance. near-data processing (NDP) is one of the effective approaches to addressing this write-amplification issue. Most NDP-based techniques adopt synchronous parallel schemes to perform a compaction task on both the host and its NDP-enabled device. In synchronous parallel compaction schemes, the execution time of compaction is determined by a subsystem that has lower compaction performance coupled by under-utilized computing resources in a NDP framework. To solve this problem, we propose an asynchronous parallel scheme named PStore to improve the compaction performance in KV stores. In PStore, we designed a multi-tasks queue and three priority-based scheduling methods. PStore elects proper compaction tasks to be offloaded in host- and device-side compaction modules. Our proposed cross-leveled compaction mechanism mitigates write amplification induced by asynchronous compaction. PStore featured with the asynchronous compaction mechanism fully utilizes computing resources in both host- and device-side subsystems. Compared with the two popular synchronous compaction modes based on KV stores (TStore and LevelDB), our PStore immensely improves the throughput by up to a factor of 14 and 10.52 with an average of a factor of 2.09 and 1.73, respectively.

关键词： near-data processing key-value store asynchronous compaction write amplification

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GraNDe: Efficient near-data processing Architecture for Graph Neural Networks

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IEEE TRANSACTIONS ON COMPUTERS 2024年第10期73卷 2391-2404页

作者： Yun, Sungmin Nam, Hwayong Park, Jaehyun Kim, Byeongho Ahn, Jung Ho Lee, Eojin Seoul Natl Univ Seoul 08826 South Korea Samsung Elect Suwon 16677 South Korea Inha Univ Inchon 22212 South Korea

Graph Neural Network (GNN) models have attracted attention, given their high accuracy in interpreting graph data. One of the primary building blocks of a GNN model is aggregation, which gathers and averages the feature vectors corresponding to the nodes adjacent to each node. Aggregation works by multiplying the adjacency and feature matrices. The size of both matrices exceeds the on-chip cache capacity for many realistic datasets, and the adjacency matrix is highly sparse. These characteristics lead to little data reuse, causing intensive main-memory accesses during the aggregation process. Thus, aggregation exhibits memory-intensive characteristics and dominates most of the total execution time. In this paper, we propose GraNDe, an NDP architecture that accelerates memory-intensive aggregation operations by locating NDP modules near DRAM datapath to exploit rank-level parallelism. GraNDe maximizes bandwidth utilization by separating the memory channel path with the buffer chip in between so that pre-/post-processing in the host processor and reduction in NDP modules operate simultaneously. By exploring the preferred data mappings of the operand matrices to DRAM ranks, we architect GraNDe to support adaptive matrix mapping that applies the optimal mapping for each layer depending on the dimension of the layer and the configuration of a memory system. We also propose adj-bundle broadcasting and re-tiling optimizations to reduce the transfer time for adjacency matrix data and to improve feature vector data reusability by exploiting tiling with consideration of adjacency between nodes. GraNDe achieves 3.01x and 1.69x on average, and up to 4.00x and 1.98x speedups of GCN aggregation over the baseline system and the state-of-the-art NDP architecture for GCN, respectively.

关键词： Graph neural networks Sparse matrices Random access memory Computer architecture Bandwidth Symmetric matrices Memory management near-data processing DRAM graph neural networks

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Collaborative Compaction Optimization System using near-data processing for LSM-tree-based Key-Value Stores

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2019年第0期131卷 29-43页

作者： Sun, Hui Liu, Wei Huang, Jianzhong Shi, Weisong Anhui Univ Sch Comp Sci & Technol Key Lab Intelligent Comp & Signal Proc Minist Educ Hefei 230601 Anhui Peoples R China Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Hubei Peoples R China Wayne State Univ Dept Comp Sci Detroit MI 48202 USA

Log-structured merge tree (LSM-tree) based key-value stores are widely employed in large-scale storage systems. In compaction, high-level sorted string table files (i.e., SSTables) are merged with low-level overlapping key ranges and sorted for data queries. However, the compaction process incurs write amplification, which degrades system performance particularly under update-intensive workloads. Current optimizations mostly focus on reducing the overload of compaction in the host but rarely exploit parallelisms between the host and the device to fully utilize computing resources in the entire system for optimizing compaction performance. In this study, we propose Co-KV, a Collaborative Key-Value store, to improve compaction performance in LSM-tree-based key-value stores. Co-KV is based on a near-data processing (i.e., NDP) model-enabled storage device. Co-KV exhibits the following advantages: (1) it reduces write amplification and host-side CPU costs using a compaction offloading scheduling between a host computer and an NDP-enabled storage device;(2) it relieves the overload associated with data transfer between the host and the storage device;and (3) it improves the compaction of LSM-tree based key-value stores under update-intensive workloads. We employed an Open Ethernet Driver (OED), which is a real-world NDP platform as the testbed for our experiments. Extensive db_bench evaluations demonstrate that Co-KV achieves overall throughput improvements of approximately 1.75x, CPU cost reductions of approximately 68.1%, and write amplification reductions by up to 50.0% over the state-of-the-art LevelDB. Under YCSB workloads, Co-IN increases throughput by 1.7x similar to 1.9x while decreasing the write amplification and average latency by up to 50.0% and 46.3%, respectively. (C) 2019 Elsevier Inc. All rights reserved.

关键词： LSM-tree Key-value store near-data processing Compaction Partitioning Offloading

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NDPGNN: A near-data processing Architecture for GNN Training and Inference Acceleration

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第11期43卷 3997-4008页

作者： Wang, Haoyang Zhang, Shengbing Fan, Xiaoya Yang, Zhao Zhang, Meng Northwestern Polytech Univ Sch Comp Sci Xian 710072 Peoples R China Changan Univ Coll Future Transportat Xian 710064 Peoples R China

Graph neural networks (GNNs) require a large number of fine-grained memory accesses, which results in inefficient use of bandwidth resources. In this article, we introduce a near-data processing architecture tailored for GNN acceleration, named NDPGNN. NDPGNN provides different operating modes to meet the acceleration needs of various GNN frameworks while ensuring the configurability and scalability of the system. NDPGNN takes advantage of data locality characteristics to repeatedly distribute and utilize data, thereby reducing memory access requirements, and further improving memory access efficiency by combining a subgraph sparse node scheduling strategy with intermediate result reuse. We use data packaging to provide a higher effective data ratio for long-distance data transmission, thereby improving the utilization of the system's limited bandwidth resources. Compared with the previous method, NDPGNN brings 5.68 times improvement in system performance while reducing energy consumption overhead by 8.49 times.

关键词： Training Integrated circuits Energy consumption Design automation System performance Scalability Memory management Bandwidth Packaging Graph neural networks Graph neural networks (GNNs) hardware accelerator near-data processing

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