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55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Tiuangfu, Wenqin Malladi, Krishna T. Chang, Andrew Xie, Yuan Univ Calif Santa Barbara Santa Barbara CA 93106 USA Samsung Semicond Inc San Jose CA USA

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

Genome analysis benefits precise medical care, wildlife conservation, pandemic treatment (e.g., COVID-19), and so on. Unfortunately, in genuine analysis, the speed of data processing lags far behind the speed of data generation. Thus, hardware acceleration turns out to be necessary. As many applications in genome analysis arc memorybound, processing-In-Memory (PIM) and near-data-processing (NDP) solutions have been explored to tackle this problem. In particular, the Dual-Inline-Memory-Module (DIMM) based designs are very promising due to their non-invasive feature to the cost-sensitive DRAM dies. However, they have two critical limitations, i.e., performance bottle-necked by communication and the limited potential for memory expansion. In this paper, we address these two limitations by designing novel DIMM based accelerators located near the dis-aggregated memory pool with the support from the Compute Express Link (CXL), aiming to leverage the abundant memory within the memory pool and the high communication bandwidth provided by CXL. We propose BEACON, Scalable near-data-processing Accelerators for Genome Analysis near Memory fool with the CXL Support. BEACON adopts a software-hardware co-design approach to tackle the above two limitations. The BEACON architecture builds the foundation for efficient communication and memory expansion by reducing data movement and leveraging the high communication bandwidth provided by CXL. Based on the BEACON architecture, we propose a memory management framework to enable memory expansion with unmodified CXL-DIMMs and further optimize communication by improving data locality. We also propose algorithm-specific optimizations to further boast the performance of BEACON. In addition, BEACON provides two design choices, i.e., BEACON-D and BEACON-S. BEACON-D and BEACON-S perform the computation within the enhanced CXL-DIMMs and enhanced CXL-Switches, respectively. Experimental results show that compared with state-of-the-art DIMM based

关键词： genome analysis near-data-processing software-hardware co-design accelerator memory dis-aggregation

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Concurrent data Structures with near-data-processing: an Architecture-Aware Implementation 19

Concurrent Data Structures with Near-Data-Processing: an Arc...

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31st ACM Symposium on Parallelism in Algorithms and Architecturess (SPAA)

作者： Choe, Jiwon Huang, Amy Moreshet, Tali Herlihy, Maurice Bahar, R. Iris Brown Univ Providence RI 02912 USA Boston Univ Boston MA 02215 USA

ISBN: (纸本)9781450361842

Recent advances in memory architectures have provoked renewed interest in near-data-processing (NDP) as way to alleviate the "memory wall" problem. An NDP architecture places logic circuits, such as simple processors, in close proximity to memory. Effective use of NDP architectures requires rethinking data structures and their algorithms. Here, we provide an empirical evaluation of several NDP-aware algorithms for general-purpose concurrent data structures such as linked-lists, skiplists, and FIFO queues. The empirical analysis reveals that the potential benefits of NDP-based concurrent data structures are less than what had been expected in earlier studies. In turn, we introduce lightweight NDP hardware modifications, inspired by initial observations on data access patterns and underlying DRAM activity. Even the minimal changes to hardware significantly improve the performance and energy consumption of NDP-based concurrent data structures, and in many cases, the resulting data structures outperform state-of-the-art concurrent data structures.

关键词： near-data-processing hardware-software co-design concurrent data structures

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BEACON: Scalable near-data-processing Accelerators for Genome Analysis near Memory Pool with the CXL Support 22

BEACON: Scalable Near-Data-Processing Accelerators for Genom...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Wenqin Huangfu Krishna T. Malladi Andrew Chang Yuan Xie University of California Santa Barbara Samsung Semiconductor Inc.

ISBN: (纸本)9781665462723

Genome analysis benefits precise medical care, wildlife conservation, pandemic treatment (e.g., COVID-19), and so on. Unfortunately, in genome analysis, the speed of data processing lags far behind the speed of data generation. Thus, hardware acceleration turns out to be *** many applications in genome analysis are memory-bound, processing-In-Memory (PIM) and near-data-processing (NDP) solutions have been explored to tackle this problem. In particular, the Dual-Inline-Memory-Module (DIMM) based designs are very promising due to their non-invasive feature to the cost-sensitive DRAM dies. However, they have two critical limitations, i.e., performance bottle-necked by communication and the limited potential for memory *** this paper, we address these two limitations by designing novel DIMM based accelerators located near the dis-aggregated memory pool with the support from the Compute Express Link (CXL), aiming to leverage the abundant memory within the memory pool and the high communication bandwidth provided by CXL. We propose BEACON, Scalable near-data-processing Accelerators for Genome Analysis near Memory Pool with the CXL Support. BEACON adopts a software-hardware co-design approach to tackle the above two limitations. The BEACON architecture builds the foundation for efficient communication and memory expansion by reducing data movement and leveraging the high communication bandwidth provided by CXL. Based on the BEACON architecture, we propose a memory management framework to enable memory expansion with unmodified CXL-DIMMs and further optimize communication by improving data locality. We also propose algorithm-specific optimizations to further boost the performance of BEACON. In addition, BEACON provides two design choices, i.e., BEACON-D and BEACON-S. BEACON-D and BEACON-S perform the computation within the enhanced CXL-DIMMs and enhanced CXL-Switches, respectively. Experimental results show that compared with state-of-the-art DIMM based ND

关键词： genome analysis near-data-processing software-hardware co-design accelerator memory dis-aggregation

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near data processing Performance Improvement Prediction via Metric-Based Workload Classification 11

Near Data Processing Performance Improvement Prediction via ...

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11th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Papalekas, Dimitrios Tziouvaras, Athanasios Floros, George Univ Thessaly Elect & Comp Engn Volos Greece

ISBN: (数字)9781665467179

ISBN: (纸本)9781665467179

Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. data-Intensive applications such as Machine Learning and Graph processing algorithms depend on time and energy consuming transactions between the memory bus and the CPU caches. The emergence of 3D-Stacked memories that provide a very high bandwidth led to the exploration of the Process-In-Memory (PIM) paradigm where logic is added to the memory die and data are being processed where they reside. To fully exploit this model, there is a need to methodically determine the portions of code that are better fitted for near-data-processing (NDP). To this extend, in this work, after presenting the key trends of the research field and examine proposed criteria, we simplify the process of a priori decision of a block's suitability by proposing a two-step metric-based application categorization able to predict the applications behavior when offloaded for NDP.

关键词： near-data-processing processing-In-Memory 3D-Stacked memories

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MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System

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JOURNAL OF SIGNAL processing SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2021年第6期93卷 659-675页

作者： Asgari, Bahar Mukhopadhyay, Saibal Yalamanchili, Sudhakar Georgia Inst Technol Sch Elect & Comp Engn 266 Ferst Dr NWKACB 2316 Atlanta GA 30332 USA

As computations in machine-learning applications are increasing simultaneously along the size of datasets, the energy and performance costs of data movement dominate that of compute. This issue is more pronounced in embedded systems with limited resources and energy. Although near-data-processing (NDP) is pursued as an architectural solution, comparatively less attention has been focused on how to scale NDP for larger-scale embedded machine learning applications (e.g., speech and motion processing). We propose machine-learning hardware acceleration using a software-defined intelligent memory system (Mahasim). Mahasim is a scalable NDP-based memory system, in which application performance scales with the size of data. The building blocks of Mahasim are the programable memory slices, supported by data partitioning, compute-aware memory allocation, and an independent in-memory execution model. For recurrent neural networks, Mahasim shows up to 537.95 GFLOPS/W energy efficiency and 3.9x speedup, when the size of the system increases from 2 to 256 memory slices, which indicates that Mahasim favors larger problems.

关键词： Machine learning Neural networks near-data-processing Memory system

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Making Better Use of processing-in-Memory Through Potential-Based Task Offloading

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IEEE ACCESS 2020年 8卷 61631-61641页

作者： Kim, Byoung-Hak Rhee, Chae Eun Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea

There is an increasing demand for a novel computing structure for data-intensive applications such as artificial intelligence and virtual reality. The processing-in-memory (PIM) is a promising alternative to reduce the overhead caused by data movement. Many studies have been conducted on the utilization of the PIM taking advantage of the bandwidth increased by the through silicon via (TSV). One approach is to design an optimized PIM architecture for a specific application, the other is to find the tasks that will be more advantageous when offloading to PIM. The goal of this paper is to make the PIM, a newly introduced technology, be easily applied to various applications. The programmable GPU-based PIM is the target system. The essential but simple task offloading conditions are proposed to secure as many candidate tasks as possible when there is any potential benefit from the PIM. The PIM design options then are explored reflecting the characteristics of the candidate tasks actively. When determining offloading conditions, it is difficult to simultaneously consider three time-energy-power objectives. Thus, the problem is divided into two sub-problems. The first offloading condition is designed based on time-energy constraints, whereas the second offloading condition is modeled to satisfy time-power constraints. During the whole processes, the offloading conditions and the PIM design options are carefully configured in a complementary manner to reduce the tasks that are excluded from the offloading. In the simulation results, the suitability of the modeled two offloading conditions and the proposed PIM design are verified using various benchmarks and then, they are compared with previous works in terms of processing speed and energy.

关键词： High bandwidth memory near-data-processing processing-in-memory task offloading

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