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FSS: algorithm and neural network accelerator for style transfer

Science China(Information Sciences) 2024年第2期67卷 253-266页

作者： Yi LING Yujie HUANG Yujie CAI Zhaojie LI Mingyu WANG Wenhong LI Xiaoyang ZENG State Key Laboratory of ASIC & System Fudan University Shanghai Explore X Technology Co. Ltd.

neural networks(NNs), owing to their impressive performance, have gradually begun to dominate multimedia processing. For resource-constrained and energy-sensitive mobile devices, an efficient NN accelerator is necessary. Style transfer is an important multimedia application. However, existing arbitrary style transfer networks are complex and not well supported by current NN accelerators, limiting their application on mobile devices. Moreover, the quality of style transfer needs improvement. Thus, we design the Fast Style system(FSS), where a novel algorithm and an NN accelerator are proposed for style transfer. In FSS, we first propose a novel arbitrary style transfer algorithm, Fast Style. We propose a light network that contributes to high quality and low computational complexity and a prior mechanism to avoid retraining when the style changes. Then, we redesign an NN accelerator for Fast Style by applying two improvements to the basic NVIDIA deep learning accelerator(NVDLA) architecture. First, a flexible dat FSM and wt FSM are redesigned to enable the original data path to perform other operations(including the GRAM operation)by software programming. Moreover, statistics and judgment logic are designed to utilize the continuity of a video stream and remove the data dependency in the instance normalization, which improves the accelerator performance by 18.6%. The experimental results demonstrate that the proposed Fast Style can achieve higher quality with a lower computational cost, making it more suitable for mobile devices. The proposed NN accelerator is implemented on the Xilinx VCU118 FPGA under a 180-MHz clock. Experimental results show that the accelerator can stylize 512×512-pixel video with 20 FPS, and the measured performance reaches up to 306.07 GOPS. The ASIC implementation in TSMC 28 nm achieves about 22 FPS in the case of a 720-p video.

关键词： neural network accelerator style transfer neural network deep learning

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Tanji: a General-purpose neural network accelerator with Unified Crossbar Architecture

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2020年第1期37卷 56-63页

作者： Zhu, Haozhe Wang, Yu Shi, C. -J. Richard Fudan Univ Shanghai Peoples R China Univ Washington Elect & Comp Engn Seattle WA 98195 USA

Editor's note: TK

关键词： Computer architecture neural networks Convolution Kernel System-on-chip Bandwidth Unicast neural network accelerator multi-type neural network deep learning crossbar architecture

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A 22-nm All-Digital Time-Domain neural network accelerator for Precision In-Sensor Processing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第12期32卷 2220-2231页

作者： Mohey, Ahmed M. Leslin, Jelin Singh, Gaurav Kosunen, Marko Ryynanen, Jussi Andraud, Martin Aalto Univ Dept Elect & Nanoengn Espoo 02150 Finland UCLouvain ICTEAM B-1348 Leuven Belgium

Deep neural network (DNN) accelerators are increasingly integrated into sensing applications, such as wearables and sensor networks, to provide advanced in-sensor processing capabilities. Given wearables' strict size and power requirements, minimizing the area and energy consumption of DNN accelerators is a critical concern. In that regard, computing DNN models in the time domain is a promising architecture, taking advantage of both technology scaling friendliness and efficiency. Yet, time-domain accelerators are typically not fully digital, limiting the full benefits of time-domain computation. In this work, we propose an all-digital time-domain accelerator with a small size and low energy consumption to target precision in-sensor processing like human activity recognition (HAR). The proposed accelerator features a simple and efficient architecture without dependencies on analog nonidealities such as leakage and charge errors. An eight-neuron layer (core computation layer) is implemented in 22-nm FD-SOI technology. The layer occupies 70x70 mu m while supporting multibit inputs (8-bit) and weights (8-bit) with signed accumulation up to 18 bits. The power dissipation of the computation layer is 576 mu W at 0.72-V supply and 500-MHz clock frequency achieving an average area efficiency of 24.74 GOPS/mm(2) (up to 544.22 GOPS/mm(2)), an average energy efficiency of 0.21 TOPS/W (up to 4.63 TOPS/W), and a normalized energy efficiency of 13.46 1b-TOPS/W (up to 296.30 1b-TOPS/W).

关键词： Human activity recognition Neurons Accuracy Time-domain analysis Computational modeling Artificial neural networks Computer architecture Wearable devices Energy efficiency Sensors Edge computing human activity recognition (HAR) inertial measurement unit (IMU) in-sensor processing multiply-and-accumulate multiply and accumulate (MAC) neural network accelerator smart sensor interface time-domain signal processing

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A 65-nm Energy-Efficient Interframe Data Reuse neural network accelerator for Video Applications

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2022年第8期57卷 2574-2585页

作者： Yang, Yixiong Liu, Yongpan Yuan, Zhe Sun, Wenyu Liu, Ruoyang Wang, Jingyu Yue, Jinshan Feng, Xiaoyu Yuan, Zhuqing Li, Xueqing Yang, Huazhong Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Shenzhen Int Grad Sch Shenzhen 518071 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Pi2Star Technol Ltd Beijing 100083 Peoples R China

An energy-efficient convolutional neural network (CNN) accelerator is proposed for the video application. Previous works exploited the sparsity of differential (Diff) frame activation, but the improvement is limited as many Diff-frame data is small but non-zero. Processing of irregular sparse data also leads to low hardware utilization. To solve these problems, two key innovations are proposed in this article. First, we implement a hybrid-precision inter-frame-reuse architecture which takes advantage of both low bit-width and high sparsity of Diff-frame data. This technology can accelerate 3.2x inference speed with no accuracy loss. Second, we design a conv-pattern-aware processing array that achieves the 2.48x-14.2x PE utilization rate to process sparse data for different convolution kernels. The accelerator chip was implemented in 65-nm CMOS technology. To the best of our knowledge, it is the first silicon-proven CNN accelerator that supports inter-frame data reuse. Attributed to the inter-frame similarity, this video CNN accelerator reaches the minimum energy consumption of 24.7 mu J/frame in the MobileNet-slim model, which is 76.3% less than the baseline.

关键词： Convolutional neural networks Kernel Task analysis Convolution Arrays Technological innovation Parallel processing Activation sparsity hybrid precision interframe data reuse neural network accelerator video

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Optimized co-scheduling of mixed-precision neural network accelerator for real-time multitasking applications

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JOURNAL OF SYSTEMS ARCHITECTURE 2020年 110卷 101775-101775页

作者： Jiang, Wei Song, Ziwei Zhan, Jinyu He, Zhiyuan Wen, Xiangyu Jiang, Ke Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Veoneer Sweden AB Vargarda Sweden

neural networks are increasingly applied into real-time and embedded Artificial Intelligent (AI) systems like autonomous driving system. Such resource-constrained systems cannot support the execution of neural network based tasks due to their high execution overheads on general processors. Hence, we are approaching to design realtime AI applications on embedded systems with CPU and FPGA (Field Programmable Gate Array) coprocessors. We use dedicated FPGA to accelerate the neural network job and utilize CPU to process the rest jobs of real-time multitasking applications. We devise an Idle-Aware Earliest Deadline First policy to co-schedule the AI applications on hybrid CPU and FPGA coprocessors. Since the implementation of neural network job on FPGA accelerator with different precision configuration will result in different execution time and accuracy, we are also interested in the design optimization of real-time AI applications running on mixed-precision neural network accelerator, with the purpose of maximizing the accuracy related rewards of all applications subject to real-time related constraints. We address the problem as a multi-stage decision procedure, and propose an efficient dynamic programming approach with two pruning policies to reduce the intermediate searching states. Extensive experiments and real-life case evaluations demonstrate the efficiency of the proposed approaches.

关键词： neural network accelerator Mixed-precision Real-time multitasking application Co-scheduling Design optimization

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Nonlinear Weight Quantification for Mitigating Stress Induced Disturb Effect on Multilevel RRAM-Based neural network accelerator

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2021年 9卷 1257-1261页

作者： Wu, Lindong Yu, Zhizhen Qin, Yabo Chen, Qingyu Cai, Yimao Huang, Ru Peking Univ Inst Microelect Beijing 100871 Peoples R China

The RRAM-based array is one of the most promising core functional primitives to accelerate the inference process of neural networks. However, the stress-induced disturbance can cause a significant accuracy drop during inference process where input vectors with different voltage levels are fed to the device. This kind of disturb can hardly be avoided by optimizing the fabrication process. Here, we investigate this phenomenon based on TaOx-based devices with different electrodes. The results indicate that the stress-induced disturb mainly appears in the intermediate resistance states when the voltage is applied on the device. The simulation result by COMSOL reveals the relationship between read disturb and electric field. Therefore, we propose a nonlinear weight quantification method to mitigate read disturb effect on inference accuracy by reducing the number of devices in intermediate resistance states. The simulation results based on the fully-connected networks for MNIST recognition indicate that stress disturb phenomenon can be well suppressed by nonlinear weight quantification compared with the conventional linear quantification method, which will advance the application of the RRAM-based accelerator.

关键词： Resistance Voltage measurement neural networks Simulation Object recognition Electron devices Electrodes Read disturb multilevel RRAM nonlinear weight quantification neural network accelerator

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Design space exploration of neural network accelerator based on transfer learning

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High Technology Letters 2023年第4期29卷 416-426页

作者：吴豫章 ZHI Tian SONG Xinkai LI Xi School of Computer Science University of Science and Technology of ChinaHefei 230027P.R.China State Key Lab of Processors Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China

With the increasing demand of computational power in artificial intelligence(AI)algorithms,dedicated accelerators have become a ***,the complexity of hardware architectures,vast design search space,and complex tasks of accelerators have posed significant ***-ditional search methods can become prohibitively slow if the search space continues to be expanded.A design space exploration(DSE)method is proposed based on transfer learning,which reduces the time for repeated training and uses multi-task models for different tasks on the same *** proposed method accurately predicts the latency and energy consumption associated with neural net-work accelerator design parameters,enabling faster identification of optimal outcomes compared with traditional *** compared with other DSE methods by using multilayer perceptron(MLP),the required training time is *** experiments with other methods demonstrate that the proposed method improves the efficiency of DSE without compromising the accuracy of the re-sults.

关键词： design space exploration(DSE) transfer learning neural network accelerator multi-task learning

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Approximate Logic Synthesis in the Loop for Designing Low-Power neural network accelerator 53

Approximate Logic Synthesis in the Loop for Designing Low-Po...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Qian, Yifan Meng, Chang Zhang, Yawen Qian, Weikang Wang, Runsheng Huang, Ru Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai Peoples R China Peking Univ Inst Microelect Beijing Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai Peoples R China Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781728192017

Approximate computing is an emerging circuit design paradigm. It improves the energy efficiency of circuits by introducing some errors. Recent works propose to apply approximate multipliers to design low-power neural network (NN) accelerators. Different from existing methods, in this paper, we advocate a method that integrates approximate logic synthesis (ALS) into the design loop of low-power NN accelerators. ALS automatically synthesizes a good approximate circuit and can take input distribution into consideration. With the help of ALS, the NN computation pattern can be exploited to design an approximate multiplier that fits better with the NN. The experimental results show that the proposed method can generate an extremely small approximate multiplier with area only 4:2% of the accurate version, while it can still achieve a high accuracy of 97.9% for LeNet-5 on MNIST dataset.

关键词： Approximate Computing Approximate Logic Synthesis neural network neural network accelerator

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ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic neural network accelerator 23

ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Ph...

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Li, Shurui Yang, Hangbo Wong, Chee Wei Sorger, Volker J. Gupta, Puneet Univ Calif Los Angeles Los Angeles CA 90024 USA Univ Florida Gainesville FL USA

ISBN: (纸本)9798400703294

In recent years, there has been a significant focus on achieving lowlatency and high-throughput convolutional neural network (CNN) inference. Integrated photonics offers the potential to substantially expedite neural networks due to its inherent low-latency properties. Recently, on-chip Fourier optics-based neural network accelerators have been demonstrated and achieved superior energy efficiency for CNN acceleration. By incorporating Fourier optics, computationally intensive convolution operations can be performed instantaneously through on-chip lenses at a significantly lower cost compared to other on-chip photonic neural network accelerators. This is thanks to the complexity reduction offered by the convolution theorem and the passive Fourier transforms computed by on-chip lenses. However, conversion overhead between optical and digital domains and memory access energy still hinder overall efficiency. We introduce ReFOCUS, a Joint Transform Correlator ( JTC) based on-chip neural network accelerator that efficiently reuses light through optical buffers. By incorporating optical delay lines, wavelength-division multiplexing, dataflow, and memory hierarchy optimization, ReFOCUS minimizes both conversion overhead and memory access energy. As a result, ReFOCUS achieves 2x throughput, 2.2x energy efficiency, and 1.36x area efficiency compared to state-of-the-art photonic neural network accelerators.

关键词： Photonic neural network on-chip photonics Fourier optics 4F system deep learning neural network accelerator

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VLSI Implementation of Area-Efficient Parallelized neural network accelerator Using Hashing Trick 16

VLSI Implementation of Area-Efficient Parallelized Neural Ne...

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16th International System-on-Chip Design Conference (ISOCC)

作者： Yoo, Tae Koan Park, Jong Kang Kim, Jong Tae Sungkyunkwan Univ Dept Elect & Comp Engn Suwon South Korea

ISBN: (纸本)9781728124780

Recently, neural network accelerator has adopted model compression for embedded devices which have limited constraint such as area and power dissipation. However, area efficiency has not been seriously considered for those performances. Among model compression techniques, hashing trick requires the least weight data. Thus, using hashing trick, this paper proposes neural network accelerator whose performance is comparable to others, but its circuit complexity is reduced for an embedded device. With design exploration, we considered various design models, and determined target design and parallel factors for it. For 32nm cell library, our design operated at 200Mhz could be estimated in 32.06mm(2) chip area.

关键词： quantization hashing trick neural network accelerator

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