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25th International Conference on Field Programmable Logic and Applications

作者： Andrade, Joao George, Nithin Karras, Kimon Novo, David Silva, Vitor Ienne, Paolo Falcao, Gabriel Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781467381239

HLS tools have been introduced with the promise of easening and shortening the design cycle of tedious and error-prone RTL-based development of hardware accelerators. However, they do so either by concealing meaningful hardware decisions which model the computing architecture-such as OpenCL compilers-or by abstracting them away into a high-level programming language-usually C-based. In this paper, we show that although Vivado HLS is sufficiently mature to generate a functionally correct FPGA accelerator from a naive description, reaching an accelerator which optimizes the FPGA resource utilization in a way that conveys maximum performance is a process for a hardware architect mindset. We use a highly demanding application, that requires real-time operation, and develop a non-binary ldpc decoder on a state-of-the-art Virtex 7 FPGA, using the Vivado HLS framework. Despite using the same programming syntax as a C-language software compiler, the underlying programming model is not the same, thus, the optimizations required in code refactoring are distinct. Moreover, directive-based optimizations that tweak the synthesized C description hardware must be used in order to attain efficient architectures. These processes are documented in this paper, to guide the reader on how an HLS-based accelerator can be designed, which in our case can come close to the performance achieved with dedicated hand-made RTL descriptions.

关键词： fast hardware design high-level synthesis design space exploration Vivado HLS non-binary ldpc codes

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Fast Design Space Exploration using Vivado HLS: non-binary ldpc Decoders 23

Fast Design Space Exploration using Vivado HLS: Non-Binary L...

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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Andrade, Joao George, Nithin Karras, Kimon Novo, David Silva, Vitor Ienne, Paolo Falcao, Gabriel Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781479999699

Computing on field-programmable gate arrays (FPGAs) has been receiving continued interest as it provides high performance at relatively low power budgets, while avoiding the high non-recurring engineering (NRE) costs associated with ASIC designs. However, FPGA development is typically performed using register transfer level (RTL) languages which make the design process protracted and error-prone when compared to software design flows. To ease these problems, high-level synthesis (HLS) tools have been introduced which abstract away the RTL architecture description from the designer. In this work we explore the design space of a non-binary GF(q) low-density parity-check (ldpc) decoder using Vivado HLS and compare it with state-of-the-art RTL designs.

关键词： fast hardware design high-level synthesis design space exploration Vivado non-binary ldpc codes

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Large Girth non-binary ldpc codes Based on Finite Fields and Euclidean Geometries

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IEEE SIGNAL PROCESSING LETTERS 2009年第6期16卷 521-524页

作者： Jiang, Xueqin Lee, Moon Ho Chonbuk Natl Univ Inst Informat & Commun Chonju 561756 South Korea

This letter presents an approach to the construction of non-binary low-density parity-check (ldpc) codes based on alpha-multiplied circulant permutation matrices and hyperplanes of two different dimensions in Euclidean geometries. codes constructed by this method have large girth and high binary column weight when the order of Galois field is high. Simulation results show that these codes perform very well with fast Fourier transform (FFT) based sum-product algorithm (SPA).

关键词： Euclidean geometry non-binary ldpc codes alpha-multiplied circulant permutation matrices mu-flats

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Source Coding with Side Information at the Decoder and Uncertain Knowledge of the Correlation

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IEEE TRANSACTIONS ON COMMUNICATIONS 2014年第1期62卷 269-279页

作者： Dupraz, Elsa Roumy, Aline Kieffer, Michel Univ Paris 11 L2S CNRS SUPELEC F-91192 Gif Sur Yvette France INRIA F-35042 Rennes France Inst Univ France F-75013 Paris France

This paper considers the problem of lossless source coding with side information at the decoder, when the correlation model between the source and the side information is uncertain. Four parametrized models representing the correlation between the source and the side information are introduced. The uncertainty on the correlation appears through the lack of knowledge on the value of the parameters. For each model, we propose a practical coding scheme based on non-binary Low Density Parity Check codes and able to deal with the parameter uncertainty. At the encoder, the choice of the coding rate results from an information theoretical analysis. Then we propose decoding algorithms that jointly estimate the source vector and the parameters. As the proposed decoder is based on the Expectation-Maximization algorithm, which is very sensitive to initialization, we also propose a method to produce first a coarse estimate of the parameters.

关键词： Source coding with side information non-binary ldpc codes Expectation-Maximization algorithm

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Iterative Decoding Algorithms for a Class of non-binary Two-Step Majority-Logic Decodable Cyclic codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2014年第6期62卷 1779-1789页

作者： Chang, Hsiu-Chi Chang, Hsie-Chia Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan

This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.

关键词： Extended min-sum algorithm majority-logic decoding non-binary ldpc codes cyclic codes

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Optimized Fast Walsh-Hadamard Transform on GPUs for non-binary ldpc decoding

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PARALLEL COMPUTING 2014年第9期40卷 449-453页

作者： Andrade, Joao Falcao, Gabriel Silva, Vitor Univ Coimbra Inst Telecomunicacoes Dept Elect & Comp Engn P-3030290 Coimbra Portugal

The Fourier Transform Sum-Product Algorithm (FT-SPA) used in non-binary Low-Density Parity-Check (ldpc) decoding makes extensive use of the Walsh-Hadamard Transform (WHT). We have developed a massively parallel Fast Walsh-Hadamard Transform (FWHT) which exploits the Graphics Processing Unit (GPU) pipeline and memory hierarchy, thereby minimizing the level of memory bank conflicts and maximizing the number of returned instructions per clock cycle for different generations of graphics processors, with considerable speedup gains in FT-SPA based non-binary ldpc decoding. (C) 2014 Elsevier B.V. All rights reserved.

关键词： non-binary ldpc codes Parallel processing Walsh-Hadamard Transform

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FLEXIBLE non-binary ldpc DECODING ON FPGAS

FLEXIBLE NON-BINARY LDPC DECODING ON FPGAS

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IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Andrade, Joao Falcao, Gabriel Silva, Vitor Kasai, Kenta Univ Coimbra Inst Telecomunicacoes Dept Elect & Comp Engn P-3000 Coimbra Portugal Tokyo Inst Technol Grad Sch Sci & Engn Dept Comm & Comp Engn Tokyo Japan

ISBN: (纸本)9781479928934

Despite their ability to reach within the channel capacity in shorter codeblock lengths, non-binary ldpc codes have a higher decoding complexity that poses non-trivial barriers to their generalized adoption at algorithmic and compute-intensive levels. In this work, we propose a programmable FFT-SPA decoder that delivers high decoding throughput at low power consumptions, while retaining a design flexibility at the system level which surpasses typical VLSI descriptions, guaranteeing quick retargeting and prototyping of variants of this family of signal processing algorithms with effective decoding throughputs of up to 1 Mbit/s and potential throughputs of dozens of Mbit/s.

关键词： non-binary ldpc codes GF(q) Communications FPGA OpenCL

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Stochastic Decoding of ldpc codes over GF(q)

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IEEE TRANSACTIONS ON COMMUNICATIONS 2013年第3期61卷 939-950页

作者： Sarkis, Gabi Hemati, Saied Mannor, Shie Gross, Warren J. McGill Univ Dept Elect & Comp Engn Montreal PQ H3A 2A7 Canada Linkoping Univ Dept Elect Engn Elect Syst Div S-58183 Linkoping Sweden Technion Israel Inst Technol Dept Elect Engn IL-32000 Haifa Israel

Despite the outstanding performance of non-binary low-density parity-check (ldpc) codes over many communication channels, they are not in widespread use yet. This is due to the high implementation complexity of their decoding algorithms, even those that compromise performance for the sake of simplicity. In this paper, we present three algorithms based on stochastic computation to reduce the decoding complexity. The first is a purely stochastic algorithm with error-correcting performance matching that of the sum-product algorithm (SPA) for ldpc codes over Galois fields with low order and a small variable node degree. We also present a modified version which reduces the number of decoding iterations required while remaining purely stochastic and having a low per-iteration complexity. The second algorithm, relaxed half-stochastic (RHS) decoding, combines elements of the SPA and the stochastic decoder and uses successive relaxation to match the error-correcting performance of the SPA. Furthermore, it uses fewer iterations than the purely stochastic algorithm and does not have limitations on the field order and variable node degree of the codes it can decode. The third algorithm, NoX, is a fully stochastic specialization of RHS for codes with a variable node degree 2 that offers similar performance, but at a significantly lower computational complexity. We study the performance and complexity of the algorithms;noting that all have lower per-iteration complexity than SPA and that RHS can have comparable average per-codeword computational complexity, and NoX a lower one.

关键词： non-binary ldpc codes ldpc codes over GF(q) stochastic decoding relaxed half-stochastic decoding

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Gallager B Decoder on Noisy Hardware

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IEEE TRANSACTIONS ON COMMUNICATIONS 2013年第5期61卷 1660-1673页

作者： Yazdi, S. M. Sadegh Tabatabaei Cho, Hyungmin Dolecek, Lara Qualcomm Inc Ctr Res & Dev San Diego CA 92121 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Stanford Univ Dept Elect Engn & Comp Sci Stanford CA 94305 USA

Conventional communications theory assumes that the data transmission is noisy but the processing at the receiver is entirely error-free. Such assumptions may have to be revisited for advanced (silicon) technologies in which hardware failures are a major concern at the system-level. Hence, it is important to characterize the performance of a communication system with both noisy processing components and noisy data transmission. Coding systems based on low-density parity check (ldpc) codes are widely used for a variety of applications. In this paper, we focus on probabilistic analysis of the ldpc Gallager B decoder built out of faulty components. Using the density evolution technique, we find approximations for the optimal threshold of the decoder and the symbol error rate (SER) of the decoded sequence as functions of both the channel error rate and error rates of the decoder components, for both binary and non-binary regular ldpc codes. Furthermore, we study the convergence of the output SER and the decoding threshold of the decoder for different ranges of error rates. We verify our results using MATLAB simulations and hardware emulation of noisy decoders. Results presented in this paper can serve as systematic design guidelines in resource allocation for noisy decoders. Informed resource allocation is of particular relevance to emerging data storage and processing applications that need to maintain high levels of reliability despite hardware errors in advanced technologies.

关键词： Error analysis Gallager B algorithm faulty hardware ldpc codes non-binary ldpc codes

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Achieving Near Capacity of non-binary ldpc Coded Large MIMO Systems with a Novel Ultra Low-Complexity Soft-Output Detector

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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS 2013年第10期12卷 5185-5199页

作者： Suthisopapan, Puripong Kasai, Kenta Meesomboon, Anupap Imtawil, Virasit Khon Kaen Univ Fac Engn Dept Elect Engn Khon Kaen Thailand Tokyo Inst Technol Grad Sch Sci & Engn Dept Commun & Integrated Syst Tokyo 1528550 Japan

Recently, it has been proved that both MMSE and MF detectors are near optimal detection for large scale MIMO systems, e.g., MIMO systems with hundreds of antennas. In order to attain near capacity region with reasonable complexity, lowcomplexity detector with soft-output generation is necessary for coded large MIMO systems. We show in this paper that the nonbinary ldpc codes and well-known soft-output MMSE detector can be utilized to significantly reduce the gap to capacity. We also propose a novel soft-output MF-based detector for the non-binary ldpc coded large MIMO systems. With this proposed detector, capacity approaching performance, i.e., the gap to capacity of 1.6 dB, can be achieved with ultra low-complexity detection, e.g., just 0.28% of MMSE detection. Moreover, use of the proposed scheme in large MIMO systems is found to be robust to the presence of imperfect channel estimation and spatial fading correlation which are both the realistic scenarios for large MIMO systems.

关键词： Large MIMO systems hundreds of antennas non-binary ldpc codes MMSE detection MF detection softoutput detection.

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