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检索条件"主题词=non-binary LDPC Codes"

共 73 条记录，以下是61-70 订阅

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Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-ldpc Decoding 14

Analysis of the Dual-Threshold-Based Shrinking Scheme for Ef...

引用

14th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Tian, Jing Lin, Jun Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538682401

In this paper, the dual-threshold-based shrinking (DTBS) scheme for efficient non-binary low-density parity-check (NB-ldpc) decoding, which has been initially presented in our previous work [1], is further studied. Particularly, the TIT-MSA is an example to employ this scheme presented in [1]. Its computational complexity is theoretically analyzed in this paper. Numerical results show that more than 70% computational complexity is reduced compared with the SMSA, while the error performance loss is negligible. Besides, when considering memory consumption, we extend this scheme by setting a maximum number of kept values with an efficient searching method, and apply it to the TIT-MSA. Simulation results indicate that the new decoding algorithm achieves both comparable error performance and significant memory reduction. For example, the memory consumption is reduced by about 61% for a (256, 203) code over GF(2(8)) and about 31% for an (837, 726) code over GF(2(5)).

关键词： Error correction codes non-binary ldpc codes iterative decoding min-sum decoding algorithm low-complexity decoding

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Variable-Rate Equal-Power Waterfilling for non-binary ldpc Coded Multicarrier systems

Variable-Rate Equal-Power Waterfilling for Non-Binary LDPC C...

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21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Boccolini, Gabriele Fijalkow, Inbar Univ Cergy Pontoise ENSEA CNRS ETIS F-95000 Cergy Pontoise France

ISBN: (纸本)9781424480166

This paper presents a link adaptation strategy for non-binary ldpc code over a time-variant frequency-selective channel. The algorithm is based first on the adoption of waterfilling technique to wisely adapt the transmitted power. It is shown that as long as best subchannels are identified with the waterfilling algorithm, an equal power distribution can be applied with performance comparable to the ideal power adaptation. What it is more important is to decide which are the subchannels that should not be used in order to increase the energy efficiency of the system. The throughput is increased with the adoption of multilevel modulations that changes the rate of each subchannel depending on the channel-to-noise ratio and the quality of service required. The Galois Field GF(64) code symbols are mapped into four modulation schemes (BPSK, 4QAM, 16QAM, 64QAM) and the channel is assumed to be constant over six OFDM symbols. Simulation results are presented when a perfect channel state information is available at the transmitter and at the receiver side. In real dynamic channel environments, the performance of the system degrades due to the delay and the approximation of the feedback information. Simulation of partial channel state information scenario is also reported.

关键词： non-binary ldpc codes adaptive modulation multilevel waterfilling frequency selective channel link adaptation

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From Low-architectural Expertise Up to High-throughput non-binary ldpc Decoders: Optimization Guidelines using High-level Synthesis 25

From Low-architectural Expertise Up to High-throughput Non-b...

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25th International Conference on Field Programmable Logic and Applications

作者： Andrade, Joao George, Nithin Karras, Kimon Novo, David Silva, Vitor Ienne, Paolo Falcao, Gabriel Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781467381239

HLS tools have been introduced with the promise of easening and shortening the design cycle of tedious and error-prone RTL-based development of hardware accelerators. However, they do so either by concealing meaningful hardware decisions which model the computing architecture-such as OpenCL compilers-or by abstracting them away into a high-level programming language-usually C-based. In this paper, we show that although Vivado HLS is sufficiently mature to generate a functionally correct FPGA accelerator from a naive description, reaching an accelerator which optimizes the FPGA resource utilization in a way that conveys maximum performance is a process for a hardware architect mindset. We use a highly demanding application, that requires real-time operation, and develop a non-binary ldpc decoder on a state-of-the-art Virtex 7 FPGA, using the Vivado HLS framework. Despite using the same programming syntax as a C-language software compiler, the underlying programming model is not the same, thus, the optimizations required in code refactoring are distinct. Moreover, directive-based optimizations that tweak the synthesized C description hardware must be used in order to attain efficient architectures. These processes are documented in this paper, to guide the reader on how an HLS-based accelerator can be designed, which in our case can come close to the performance achieved with dedicated hand-made RTL descriptions.

关键词： fast hardware design high-level synthesis design space exploration Vivado HLS non-binary ldpc codes

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Rate-Adaptive non-binary-ldpc-Coded Polarization-Multiplexed Multilevel Modulation with Coherent Detection for Optically-Routed Networks

Rate-Adaptive Non-binary-LDPC-Coded Polarization-Multiplexed...

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11th International Conference on Transparent Optical Networks

作者： Arabaci, Murat Djordjevic, Ivan B. Saunders, Ross Marcoccia, Roberto M. Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA Opnext Inc Los Gatos CA 95032 USA

ISBN: (纸本)9781424448258

Adaptation to changing conditions in the transmission medium is a particularly desired property in optically-routed networks due to their heterogeneous nature. Toward this goal, we propose in this paper rate-adaptive polarization multiplexed coded multilevel modulation schemes based on non-binary quasi-cyclic low-density parity-check (ldpc) codes and coherent detection. The proposed scheme can support data rates at 100 Gb/s and beyond while offering comparably better forward error correction performance with less computational complexity than bit-interleaved coded modulation schemes. The ability to adapt changing channel conditions is achieved by exploiting the inherent structure of quasi-cyclic ldpc codes.

关键词： Rate-adaptive systems coded multilevel modulation non-binary ldpc codes quasi-cyclic codes optically-routed networks optical communications

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Fast Design Space Exploration using Vivado HLS: non-binary ldpc Decoders 23

Fast Design Space Exploration using Vivado HLS: Non-Binary L...

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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Andrade, Joao George, Nithin Karras, Kimon Novo, David Silva, Vitor Ienne, Paolo Falcao, Gabriel Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781479999699

Computing on field-programmable gate arrays (FPGAs) has been receiving continued interest as it provides high performance at relatively low power budgets, while avoiding the high non-recurring engineering (NRE) costs associated with ASIC designs. However, FPGA development is typically performed using register transfer level (RTL) languages which make the design process protracted and error-prone when compared to software design flows. To ease these problems, high-level synthesis (HLS) tools have been introduced which abstract away the RTL architecture description from the designer. In this work we explore the design space of a non-binary GF(q) low-density parity-check (ldpc) decoder using Vivado HLS and compare it with state-of-the-art RTL designs.

关键词： fast hardware design high-level synthesis design space exploration Vivado non-binary ldpc codes

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FFT-SPA non-binary ldpc DECODING ON GPU

FFT-SPA NON-BINARY LDPC DECODING ON GPU

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IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Andrade, J. Falcao, G. Silva, V. Kasai, Kenta Univ Coimbra Dept Elect & Comp Eng Inst Telecomunicacoes P-3000 Coimbra Portugal Tokyo Inst Technol Grad Sch Sci & Engn Dept Comm & Integrated Syst Tokyo Japan

ISBN: (纸本)9781479903566

It is well known that non-binary ldpc codes outperform the BER performance of binary ldpc codes for the same code length. The superior BER performance of non-binary codes comes at the expense of more complex decoding algorithms that demand higher computational power. In this paper, we propose parallel signal processing algorithms for performing the FFT-SPA and the corresponding decoding of non-binary ldpc codes over GF(q). The constraints imposed by the complex nature of associated subsystems and kernels, in particular the Check Nodes, present computational challenges regarding multicore systems. Experimental results obtained on GPU for a variety of GF(q) show throughputs in the order of 2 Mbps, which is far above from the minimum throughput required, for example, for real-time video applications that can benefit from such error correcting capabilities.

关键词： non-binary ldpc codes GF(q) Communications Error correcting codes GPU

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The Proposed Simplified Iterative Decoding for 2D-ISI Magnetic Recording Channels 5

The Proposed Simplified Iterative Decoding for 2D-ISI Magnet...

引用

IEEE 5th Information Technology and Mechatronics Engineering Conference (ITOEC)

作者： Chen, Jiayue Wang, Feng Chen, Pingping Lin, Zhijian Fuzhou Univ Coll Phys & Infounat Engn Fuzhou Peoples R China Quanzhou Nounal Univ Coll Phys & Infounat Engn Quanzhou Peoples R China

ISBN: (纸本)9781728143231;9781728143224

2D inter-symbol-interference (2D-ISI) channel models ultra-high-density magnetic recording systems, which suffer from ISI in the down track direction and inter-tack interference along the cross-track direction. These interferences seriously degrade the performance of the magnetic recording systems. Low-density parity check (ldpc) codes was used in storage systems However, although non-binary ldpc codes with log-BP decoding was designed for 2D-ISI channels, it has a drawback of a high decoding complexity. To address this issue, this paper proposes a simplified iterative decoding for 2D-ISI channels. In specific, we use extended min-sum (EMS) decoding with truncation of messages to simplify computation and optimize scale factor in outer iteration by the EXIT analysis to improve the performance. Finally, the simulated results show that the proposed scheme with reduced complexity for 2D-ISI system can maintain an approximate performance to traditional one. Even at high SNR regions, the proposed scheme will be better than previously decoding algorithm.

关键词： 2D inter-symbol-interference(2D-ISI) magnetic recording non-binary ldpc codes extended min-sum (EMS)

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FLEXIBLE non-binary ldpc DECODING ON FPGAS

FLEXIBLE NON-BINARY LDPC DECODING ON FPGAS

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IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Andrade, Joao Falcao, Gabriel Silva, Vitor Kasai, Kenta Univ Coimbra Inst Telecomunicacoes Dept Elect & Comp Engn P-3000 Coimbra Portugal Tokyo Inst Technol Grad Sch Sci & Engn Dept Comm & Comp Engn Tokyo Japan

ISBN: (纸本)9781479928934

Despite their ability to reach within the channel capacity in shorter codeblock lengths, non-binary ldpc codes have a higher decoding complexity that poses non-trivial barriers to their generalized adoption at algorithmic and compute-intensive levels. In this work, we propose a programmable FFT-SPA decoder that delivers high decoding throughput at low power consumptions, while retaining a design flexibility at the system level which surpasses typical VLSI descriptions, guaranteeing quick retargeting and prototyping of variants of this family of signal processing algorithms with effective decoding throughputs of up to 1 Mbit/s and potential throughputs of dozens of Mbit/s.

关键词： non-binary ldpc codes GF(q) Communications FPGA OpenCL

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nonbinary ldpc-coded OFDM over four/eight-mode fibers with mode-dependent loss

Nonbinary LDPC-coded OFDM over four/eight-mode fibers with m...

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25th IEEE Photonics Conference (IPC)

作者： Lin, Changyu Djordjevic, Ivan B. Zou, Ding Arabaci, Murat Cvijetic, Milorad Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA Univ Arizona Coll Opt Sci Tucson AZ 85721 USA

We propose a non-binary ldpc coded mode-multiplexed coherent optical OFDM system suitable for transmission of 1.28 Tb/s 16-QAM signals over 2000 km of few-mode fiber with mode dependent loss, in strong coupling regime.

ISBN: (纸本)9781457707339

关键词： OFDM few-mode fiber non-binary ldpc codes

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non-binary Cyclic Majority-Logic Decodable codes: an Algebraic Construction by using Genetic Algorithms

Non-Binary Cyclic Majority-Logic Decodable codes: an Algebra...

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International Conference on Advanced Communication Systems and Information Security (ACOSIS)

作者： Yatribi, Anouar Belkasmi, Mostafa Ayoub, Fouad M'rabet, Zakaria Mohammed V Univ ENSIAS SIME Lab TSE Team Rabat Morocco CRMEF LaREAMA Lab MTIC Team Kenitra Morocco

ISBN: (纸本)9781509062270

In this paper, the construction of non binary cyclic One-Step Majority-Logic decoding codes from the dual domain and idempotents is investigated. This had led us to propose a new design algorithm based on Genetic Algorithms, as an extension to previous works on the binary field. With the proposed algorithm, we were able to obtain long new non-binary cyclic OSMLD codes with high coding rates and good correction capacities. In fact, two powerful properties of the algebraic construction are provided, firstly, the designed codes have their minimal distances and dimensions calculated analyticaly, secondly, they can be decoded with a low-complexity majority-voting decoding scheme.

关键词： OSMLD codes finite fields cyclotomic cosets idempotents Mattson-Solomon non-binary ldpc codes algebraic code design Genetic algorithms

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