With the enhanced performance and convergence speed than their binary counterparts, NB-ldpc codes have been considered for emerging wireless communication and storage applications. However, one challenging issue to ap...
详细信息
With the enhanced performance and convergence speed than their binary counterparts, NB-ldpc codes have been considered for emerging wireless communication and storage applications. However, one challenging issue to apply NB-ldpc codes in low-power embedded applications is the high decoding complexities. In this paper, we propose a comprehensive message length control technique that adaptively truncates decoding messages according to the domain-specific information. The number of arithmetic operations and memory accesses can be greatly reduced with shorter decoding messages. To implement the proposed technique, we propose a sequential decoder architecture which controls the decoding message length. Evaluation results show that the proposed technique can achieve significant power reduction than the conventional techniques while maintaining the same decoding performance.
This brief presents a low-power non-binary low density parity-check decoder design exploiting domain specific information for high-throughput wireless video communication applications. The proposed technique can dynam...
详细信息
This brief presents a low-power non-binary low density parity-check decoder design exploiting domain specific information for high-throughput wireless video communication applications. The proposed technique can dynamically scale the refresh rate of DRAM according to channel conditions as well as decoding states, hence to greatly reduce the DRAM power as well as the decoder power with lower refresh overhead. Evaluation results show that the proposed technique can achieve significant decoder power saving than conventional techniques.
non-binary low density parity check （NB-ldpc） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are requi...
详细信息
non-binary low density parity check （NB-ldpc） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-ldpcdecoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.
non-binary Low-Density-Parity-Check codes (NB-ldpc) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implem...
详细信息
non-binary Low-Density-Parity-Check codes (NB-ldpc) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasicyclic NB-ldpcdecoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binaryldpc code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.
VLSI architectures for finding the first W maximum/minimum values are highly demanded in the fields of K-best MIMO detector, non-binary ldpc decoder and product-code decoder. In this paper, a VLSI architecture based o...
详细信息
ISBN:
(纸本)9783319202273;9783319202266
VLSI architectures for finding the first W maximum/minimum values are highly demanded in the fields of K-best MIMO detector, non-binary ldpc decoder and product-code decoder. In this paper, a VLSI architecture based on parallel comparing scheme is explored for finding the first W maximum/minimum values from M inputs. The place and route results using a TSMC 90-nm CMOS technology show that, despite some hardware cost, it achieves on average a 3.6x faster speed performance compared to the existing partial sorting architectures.
暂无评论