It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniformsampling to sample and process low activity signals. non-uniformsampling technique generates fewer samp...
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ISBN:
(纸本)9781467378888
It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniformsampling to sample and process low activity signals. non-uniformsampling technique generates fewer samples, which means less data to process and lower power consumption. Furthermore, asynchronous logic is known to be data-driven. It proves to be more adapted to the non-uniformsampling than synchronous logic. It is thus a better alternative to design low power data-processing circuits. In this paper, we present an overview of the non-uniformsampling scheme. It also describes the architectures of a processing function (Finite Impulse Response filter) in synchronous and asynchronous technologies. These circuits have been implemented on an Altera EP2C8 FPGA in order to extract and compare their activities profiles.
This work aims at implementing an asynchronous FIR adaptive filter, based on the Recursive Inverse (RI) adaptive algorithm. Previous work has presented the proposed adaptive filter algorithm and has shown that the alg...
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ISBN:
(纸本)9781509041961
This work aims at implementing an asynchronous FIR adaptive filter, based on the Recursive Inverse (RI) adaptive algorithm. Previous work has presented the proposed adaptive filter algorithm and has shown that the algorithm's performance is similar to that of the Recursive Least Squares (RLS) algorithm. Moreover, it offers better performance than the Transform Domain (TD) algorithms, i.e. the TD LMS with Variable Step-Size (TDVSS) in stationary environments. The asynchronous logic has been chosen because of its unique low-power characteristic towards stationary events. The asynchronous-based architecture has been designed to be fast enough to accommodate the iterative computation of the filter coefficients while being accurate to ensure a minimum number of iteration, and a fast convergence. This paper presents an overview of the proposed architecture, as well as performance comparison between the RI and the RLS algorithm. Preliminary test shows promising results, nevertheless some optimization is required to reduce the complexity of the design and to increase the accuracy of the computation.
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