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A modified extended min-sum algorithm based on posterior probability thresholding for non-binary low-density parity-check codes

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ELECTRONICS LETTERS 2022年第23期58卷 881-883页

作者： Zhao, Yatong Wang, Liqian Zhu, Miao Wang, Weiming Tao, Kai Shi, Yinlong Chen, Xue Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing Peoples R China ZTE Corp Shenzhen Peoples R China

This letter focuses on improving the error correction performance of the extended min-sum (EMS) decoding algorithm. Introducing factor/offset modifications in the check node update process of the EMS algorithm can improve the performance. Based on this, the authors propose a novel threshold-based modified EMS algorithm that introduces the factor/offset in a targeted manner by setting a threshold for the posterior probability. Simulation results show that an additional performance gain of the order of 0.08 dB is obtained with the proposed method without significantly increasing the complexity of the method.

关键词： error correction performance threshold-based modified EMS algorithm modified extended min-sum algorithm parity check codes posterior probability probability extended min-sum decoding algorithm error correction nonbinary low-density parity-check codes check node update process decoding additional performance gain

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Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

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IEEE ACCESS 2021年 9卷 74531-74538页

作者： Park, Kyeong Bin Chung, Ki-Seok Hanyang Univ Dept Elect & Comp Engn Seoul 04763 South Korea

This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms.

关键词： Reliability Error analysis Decoding Iterative decoding Hamming distance Prediction algorithms Complexity theory Error correction codes Hamming distance hard decision iterative hard-reliability-based majority-logic decoding algorithm NAND flash memory nonbinary low-density parity-check codes

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Design of nonbinary LDPC codes Based on Message-Passing Algorithms

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IEEE TRANSACTIONS ON COMMUNICATIONS 2018年第11期66卷 5028-5040页

作者： Cho, Sunghye Cheun, Kyungwhoon Yang, Kyeongcheol Pohang Univ Sci & Technol Dept Elect Engn Pohang 37673 South Korea Samsung Elect Co Ltd DRAM Design Team Memory Business Suwon 16677 South Korea Samsung Elect Co Ltd Networks Business Res & Dev Team Suwon 16677 South Korea

Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may he even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliat et al. However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say >= 5000.

关键词： nonbinary low-density parity-check codes full rank condition message-passing algorithm counting cycles error floor design method

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A Reduced Complexity Decoding Algorithm for NB-LDPC codes 17

A Reduced Complexity Decoding Algorithm for NB-LDPC Codes

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IEEE 17th International Conference on Communication Technology (ICCT)

作者： Song, Suwen Lin, Jun Tian, Jing Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781509039449

Non-binary low-density parity-check (NB-LDPC) codes perform much better than their binary counterparts, when codeword length is moderate or high-order modulation is used. However, the implementation of a NB-LDPC decoder usually suffers from excessive hardware complexity and large memory requirement. Many new algorithms and decoding schedules have been introduced in recent literatures to reduce the decoding complexity in further. However, the complexity of current decoding algorithms for NB-LDPC codes is still high. In this paper, a two-extra-column trellis min-sum algorithm (TEC-TMSA) is proposed. The TEC-TMSA combines the two-extra-column method and the trellis min-sum algorithm in an intelligent way. Since only the minimum value of a row needs to be sorted out for configuration constructions, the computational complexity of the proposed TEC-TMSA is much lower than that of the TMSA. Furthermore, we develop a novel location-fixed selection scheme, which significantly decreases the number of required comparison operations in the TEC-TMSA with negligible performance loss.

关键词： nonbinary low-density parity-check codes two-extra-colonm trellis min-sum location-fixed selection scheme low complexity

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Joint algebraic coded modulation and lattice-reduction-aided preequalisation

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ELECTRONICS LETTERS 2016年第7期52卷 523-524页

作者： Stern, S. Fischer, R. F. H. Univ Ulm Inst Commun Engn D-89069 Ulm Germany

Lattice-reduction-aided (LRA) preequalisation for the multiple-input/multiple-output broadcast channel has most often been considered for the uncoded case so far. However, recent advantages in the closely related field of integer-forcing equalisation, where the cancellation of the multiuser interference and the channel coding are combined, create doubt to this separated point of view. In this Letter, the philosophy of matching both the channel code and the complex-valued signal constellation to the same finite-field arithmetic is proposed. The consequences on the factorisation task present in LRA preequalisation are discussed and covered by numerical performance evaluations based on non-binary low-density parity-check codes.

关键词： MIMO communication algebraic codes broadcast channels channel coding equalisers interference suppression modulation coding LRA channel coding complex-valued signal constellation factorisation task finite-field arithmetic integer-forcing equalisation joint algebraic coded modulation lattice-reduction-aided preequalisation multiple-input-multiple-output broadcast channel multiuser interference cancellation nonbinary low-density parity-check codes numerical performance evaluations

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A Reduced Complexity Decoding Algorithm for NB-LDPC codes

A Reduced Complexity Decoding Algorithm for NB-LDPC Codes

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2017 17th IEEE International Conference on Communication Technology (ICCT 2017)

作者： Suwen Song Jun Lin Jing Tian Zhongfeng Wang School of Electronic Science and Engineering Nanjing University

Non-binary low-density parity-check（NB-LDPC） codes perform much better than their binary counterparts, when codeword length is moderate or high-order modulation is used. However, the implementation of a NB-LDPC decoder usually suffers from excessive hardware complexity and large memory requirement. Many new algorithms and decoding schedules have been introduced in recent literatures to reduce the decoding complexity in further. However, the complexity of current decoding algorithms for NB-LDPC codes is still high. In this paper, a two-extra-column trellis min-sum algorithm（TEC-TMSA） is proposed. The TEC-TMSA combines the twoextra-column method and the trellis min-sum algorithm in an intelligent way. Since only the minimum value of a row needs to be sorted out for configuration constructions, the computational complexity of the proposed TEC-TMSA is much lower than that of the TMSA. Furthermore, we develop a novel location-fixed selection scheme, which significantly decreases the number of required comparison operations in the TEC-TMSA with negligible performance loss.

关键词： nonbinary low-density parity-check codes twoextra-column trellis min-sum location-fixed selection scheme low complexity

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low-latency low-complexity heap-based extended min-sum algorithms for non-binary low-density parity-check codes

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IET COMMUNICATIONS 2015年第9期9卷 1191-1198页

作者： Hwang, Youngjun Yang, Kyeongcheol Cheun, Kyungwhoon Pohang Univ Sci & Technol Dept Elect Engn Pohang 790784 Gyeongbuk South Korea

The extended min-sum (EMS) and improved EMS (I-EMS) algorithms for non-binary low-density parity-check codes over GF(q) significantly reduce the decoding complexity with an acceptable performance degradation, but they suffer from high latency because of many serial computations, including a sorting process. On the other hand, the trellis-based EMS algorithm can greatly reduce the latency, but it does not solve the complexity problem in high-order fields (q >= 64). To improve the latency problem with low-complexity advantages, the authors propose heap-based EMS (H-EMS) and heap-based I-EMS (HI-EMS) algorithms that are modifications of the EMS and I-EMS algorithms, respectively. The authors also propose double H-EMS and double HI-EMS algorithms trading off the latency against the performance by heaping messages twice. Numerical results show that the H-EMS algorithm has 2.74-9.52 times lower latency than the EMS algorithm with a negligible performance degradation over a wide range of code rates, whereas the HI-EMS algorithm has 1.20-1.62 times lower latency than the I-EMS algorithm. Furthermore, the proposed algorithms may be employed regardless of the decoding schedules.

关键词： decoding parity check codes Galois fields low-latency low-complexity heap-based extended min-sum algorithms nonbinary low-density parity-check codes improved EMS algorithms I-EMS algorithms GF(q) decoding complexity reduction performance degradation sorting process trellis-based EMS algorithm heap-based EMS algorithm H-EMS algorithm heap-based I-EMS algorithm HI-EMS algorithms

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Decoding of non-binary low-density parity-check codes based on the genetic algorithm and applications over mobile fading channels

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IET COMMUNICATIONS 2015年第16期9卷 1941-1948页

作者： Liu, Xingcheng Liang, Chulong Zhang, Yuanbin Zhang, Lin Sun Yat Sen Univ Sch Informat Sci & Technol Guangzhou 510006 Guangdong Peoples R China

In this study, an efficient decoding algorithm is proposed to decode non-binary low-density parity-check (LDPC) codes. The algorithm is derived from the belief-propagation (BP) decoding with genetic algorithm of binary LDPC codes. For the proposed algorithm, two decoding constraints are introduced to determine variable nodes which are considered highly reliable. The messages from these highly reliable variable nodes are then magnified with an appropriate parameter . This process can make the messages propagate in the Tanner graph more efficiently. Simulation results show that, compared with the fast Fourier transform-based BP algorithm, the proposed algorithm can have an equal or better performance in low bit-error-rate region over both the additive white Gaussian noise channels and the mobile fading channels.

关键词： fading channels mobile computing binary codes parity check codes channel coding decoding genetic algorithms AWGN channels graph theory nonbinary low-density parity-check codes genetic algorithm mobile fading channels belief-propagation decoding algorithm binary LDPC codes variable node determination message propagation Tanner graph low bit-error-rate region additive white Gaussian noise channels

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Towards optimal edge weight distribution and construction of field-compatible low-density parity-check codes over GF(q)

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IET COMMUNICATIONS 2014年第18期8卷 3215-3222页

作者： Han, Guojun Guan, Yong Liang Kong, Lingjun Chan, Kheong Sann Cai, Kui Guangdong Univ Technol Sch Informat Engn Guangzhou 510006 Guangdong Peoples R China Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Nanjing Univ Posts & Telecommun Sch Comp Sci & Technol Nanjing 210003 Peoples R China ASTAR Data Storage Inst Singapore 117608 Singapore

Non-binary low-density parity-check (NB-LDPC) codes can be directly constructed by using algebraic methods, or indirectly constructed by mapping well-designed binary parity-check matrices to non-binary parity-check matrices. Given the Tanner graph (TG) of a NB-LDPC code, the selection of edge weights in the TG significantly affects the performance of the NB-LDPC code. The authors introduce an edge weight distribution (EWD) parameter for the TG of NB-LDPC codes. By utilising particle swarm optimisation (PSO), the EWD is optimised and it has been demonstrated that the optimal EWD approaches a two-element distribution for large field size and high average variable-node degree. With the optimised EWD, the authors construct a class of field-compatible LDPC (FC-LDPC) codes over GF(q) whose parity-check matrices only include elements 0, 1 and 2, and can be encoded and decoded over different field sizes. The simulations demonstrate that the performance of the proposed FC-LDPC codes improves monotonically with increasing field size, and significantly outperforms that of the corresponding algebraic NB-LDPC codes or NB-LDPC codes generated with uniform distribution of non-zero elements over GF(q).

关键词： parity check codes graph theory particle swarm optimisation matrix algebra algebraic codes decoding optimal edge weight distribution optimal edge weight construction field-compatible low-density parity-check codes nonbinary low-density parity-check codes algebraic methods binary parity-check matrices nonbinary parity-check matrices Tanner graph NB-LDPC code TG EWD parameter particle swarm optimisation PSO two-element distribution variable-node degree fleld-compatible LDPC codes GF(q) decoding FC-LDPC codes

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nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第6期22卷 1455-1459页

作者： Garcia-Herrero, Francisco Jose Canet, Maria Valls, Javier Univ Politecn Valencia Inst Telecomunicac & Aplicac Multimedia Gandia 46730 Spain

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations.

关键词： Error correction codes hardware architecture iterative decoding nonbinary low-density parity-check codes symbol flipping decoding

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