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Automatic classification of object code using machine learning

DIGITAL INVESTIGATION 2015年第S1期14卷 S156-S162页

作者： Clemens, John Univ Maryland Baltimore Cty Baltimore MD 21228 USA Johns Hopkins Univ Appl Phys Lab Laurel MD USA

Recent research has repeatedly shown that machine learning techniques can be applied to either whole files or file fragments to classify them for analysis. We build upon these techniques to show that for samples of un-labeled compiled computer object code, one can apply the same type of analysis to classify important aspects of the code, such as its target architecture and endianess. We show that using simple byte-value histograms we retain enough information about the opcodes within a sample to classify the target architecture with high accuracy, and then discuss heuristic-based features that exploit information within the operands to determine endianess. We introduce a dataset with over 16000 code samples from 20 architectures and experimentally show that by using our features, classifiers can achieve very high accuracy with relatively small sample sizes. (C) 2015 The Authors. Published by Elsevier Ltd on behalf of DFRWS. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/).

关键词： Machine learning Classification Computer architecture Malware analysis object code

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Symbolic object code analysis

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INTERNATIONAL JOURNAL ON SOFTWARE TOOLS FOR TECHNOLOGY TRANSFER 2014年第1期16卷 81-102页

作者： Muehlberg, Jan Tobias Luettgen, Gerald Katholieke Univ Leuven IBBT DistriNet Celestijnenlaan 200A B-3001 Leuven Belgium Univ Bamberg Software Technol Res Grp D-96045 Bamberg Germany

Software model checkers quickly reach their limits when being applied to verifying pointer safety properties in source code that includes function pointers and inlined assembly. This article introduces a novel technique for checking pointer safety violations, called symbolic object code analysis (SOCA), which is based on bounded symbolic execution, incorporates path-sensitive slicing, and employs the SMT solver Yices as its execution and verification engine. Extensive experimental results of a prototypic SOCA Verifier, using the Verisec suite and almost 10,000 Linux device driver functions as benchmarks, show that SOCA performs competitively to modern source-code model checkers, scales well when applied to real operating systems code and pointer safety issues, and effectively explores niches of pointer-complex software that current software verifiers do not reach.

关键词： Software verification Bounded model checking Program slicing object code Case study Linux device drivers

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Automated proofs of object code for a widely used microprocessor

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JOURNAL OF THE ACM 1996年第1期43卷 166-192页

作者： Boyer, RS Yu, Y DIGITAL EQUIPMENT CORP SYST RES CTR PALO ALTO CA 94301 USA

We have formally described a substantial subset of the MC68020, a widely used microprocessor built by Motorola, within the mathematical logic of the automated reasoning system Nqthm, a.k.a. the Boyer-Moore Theorem Prover [Boyer and Moore 1988]. Using this formal description, we have mechanically checked the correctness of MC68020 object code programs for binary search, Hoare's Quick Sort, twenty-one functions from the Berkeley Unix C string library, and other well-known algorithms. The object code for these examples was generated using the Gnu C, the Verdix Ada, and the Gnu Common Lisp compilers. We have mechanized a mathematical theory to facilitate automated reasoning about object code programs. We describe a two-stage methodology we use to do our proofs.

关键词： Ada automated reasoning Boyer-Moore logic C Common Lisp formal methods machine code mechanical theorem proving MC68xxx Nqthm object code program proving program verification

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Automatic classification of object code using machine learning

Automatic classification of object code using machine learni...

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15th Annual DFRWS Conference (DFRWS USA)

作者： Clemens, John Univ Maryland Baltimore Cty Baltimore MD 21228 USA Johns Hopkins Univ Appl Phys Lab Laurel MD USA

关键词： Machine learning Classification Computer architecture Malware analysis object code

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object code OPTIMIZATION

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COMMUNICATIONS OF THE ACM 1969年第1期12卷 13-&页

作者： LOWRY, ES MEDLOCK, CW International Business Machines Corp. Poughkeepsie NY International Business Machines Corp. Poughkeepsie NY

Methods of analyzing the control flow and data flow of programs during compilation are applied to transforming the program to improve object time efficiency. Dominance relationships, indicating which statements are necessarily executed before others, are used to do global common expression elimination and loop identification. Implementation of these and other optimizations in OS/360 FORTRAN H are described. [ABSTRACT FROM AUTHOR]

关键词： FORTRAN System/360 compilers data flow analysis dominance efficiency graph theory loop structure machine instructions object code optimization redundancy elimination register assignment

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ASSEMBLY LANGUAGE AS object code

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SOFTWARE-PRACTICE & EXPERIENCE 1983年第8期13卷 715-725页

作者： JONES, DW Department of Computer Science University of Iowa Iowa City Iowa 52242 U.S.A.

The set of meanings that may be encoded in most object languages is a subset of the meanings that may be encoded in most assembly languages. Careful exploitation of this fact in the design of the SMAL assembly and object language allows the SMAL assembler itself to be used as a linkage editor, thus eliminating the need for an expensive and often misunderstood system program. The SMAL assembler is no more complex than many assemblers in common use today, nor are the relevant aspects of the SMAL language particularly unique.

关键词： object code Linkers Loaders Assembly language Intermediate code Relocation

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A power reduction technique with object code merging for application specific embedded processors 00

A power reduction technique with object code merging for app...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Tohru Ishihara Hiroto Yasuura Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University 6-1 Kasuga-koen Kasuga-shi Fukuoka 816-8580 Japan

ISBN: (纸本)0769505376

In this paper, a power reduction technique which merges frequently executed sequences of abject codes into a set of single instructions is proposed. The merged sequence of object codes is restored by an instruction decompressor before decoding the object codes. The decompressor is implemented by a ROM. In many programs, only a few sequences of object codes are frequently executed. Therefore, merging these frequently executed sequences into a single instructions leads to a significant energy reduction. Our experiments with actual read only memory(ROM) modules and some benchmark program demonstrate significant energy reductions up to more than 65% at best case over a instruction memory without the object code merging.

关键词： power reduction object code instruction memory Energy conservation benchmark program merger pressure-relief device codes instruction Custom design ROM1 gene Read Only Memory Device Component

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A Logic Based Approach to Locate Composite Refactoring Opportunities in object-Oriented code

A Logic Based Approach to Locate Composite Refactoring Oppor...

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IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR)

作者： Jebelean, Calin Chirila, Ciprian-Bogdan Cretu, Vladimir Univ Politehn Timisoara Fac Automat & Comp Sci Timisoara Romania

ISBN: (纸本)9781424467259

In today's software engineering, more and more emphasis is put on the quality of object-oriented software design. It is commonly accepted that building a software system with maintainability and reusability issues in mind is far more important than just getting all the requirements fulfilled in one way or another. Design patterns are powerful means to obtain this goal. Tools have been built that automatically detect design patterns in object-oriented code and help in understanding the code. Other tools help in refactoring object-oriented code towards introducing design patterns, but human intelligence is needed to detect where these design patterns should be inserted. This paper proposes a logic approach to the automatic detection of places within object-oriented code where the Composite design pattern could have been used. Suspects identified by such a tool could very well be served as input data for other tools that automatically refactor the code as to introduce the missing design pattern.

关键词： design pattern object orientation codes object code automatic detection Software systems Maintainability Formal logic

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AUTOMATIC GENERATION OF object-ORIENTED code FROM DEVS GRAPHICAL SPECIFICATIONS

AUTOMATIC GENERATION OF OBJECT-ORIENTED CODE FROM DEVS GRAPH...

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Winter Simulation Conference (WSC)

作者： Hamri, M. Zacharewicz, G. Aix Marseille Univ LSIS UMR 7296 Ave Escadrille Normandie Niemen F-13397 Marseille 20 France Univ Bordeaux 1 CNRS IMS LAPS F-33405 Talence France

ISBN: (纸本)9781467347792;9781467347808

paper presents an approach to automatically generate object-oriented code from DEVS graphical model specification. Afterward the generated DEVS code is given to the LSIS_DME DEVS simulator to execute the corresponding behavior. This research is driven by the idea that the user of M&S, even not computer scientist and/or beginner in formal modeling like DEVS can increase his trust in the models he creates and the simulation results he is able to obtain due to the fact he is directly involved at the modeling stage and not anymore interfaced with an intermediate actor (modeler or programmer expert) that would interpret user requirements in the modeling and simulation activities. Using the proposed tool with its user friendly framework and appropriate graphical items, the user is capable to skip learning installation set up and user manual to rapidly develop his own DEVS models, to carry out simulations and to analyze them.

关键词： autogeneration object orientation object code Computer personnel codes User needs Specifications helium Modeling Nonprofit Organizations trust Trust

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Specifying representations of machine instructions

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ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS 1997年第3期19卷 492-524页

作者： Ramsey, N Fernandez, MF AT&T LABS RES FLORHAM PK NJ 07932 USA

We present SLED, a Specification Language for Encoding and Decoding, which describes abstract, binary, and assembly-language representations of machine instructions. Guided by a SLED specification, the New Jersey Mathine-code Toolkit generates bit-manipulating code for use in applications that process machine code, Programmers can write such applications at an assembly-language level of abstraction, and the toolkit enables the applications to recognize and emit the binary representations used by the hardware, SLED is suitable for describing both CISC and RISC machines;Re have specified representations of MIPS R3000, SPARC, Alpha, and Intel Pentium instructions, and toolkit users have written specifications for the Power PC and Motorola 68000. The article includes representative excerpts from our SPARC and Pentium specifications. SLED uses four elements;fields and tokens describe parts of instructions;patterns describe binary representations of instructions or groups of instructions;and constructors map between the abstract and binary levels. By combining the elements in different ways, SLED supports machine-independent implementations of machine-level concepts like conditional assembly, span-dependent instructions, relocatable addresses, object code, sections, and relocation SLED specifications can be checked automatically for consistency with existing assemblers. The implementation of the toolkit is largely determined by our representations of patterns and constructors. We use a normal form that facilitates construction of encoders and decoders. The article describes the normal form and its use. The toolkit has been used to help build several applications. We have Guilt a retargetable debugger and a retargetable, optimizing linker. Colleagues have built a dynamic code generator, a decompiler, and an execution-time analyzer. The toolkit generates efficient code;for example, the linker emits binary up to 15% faster than it emits assembly language, making it 1.7-2 tim

关键词： compiler generation decoding encoding machine code machine description object code relocation

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