The paper depicts nowadays approach for object-oriented hardware modeling, synthesis, implementation, and management. Implementation is realized for the control and diagnosis class of multichannel, distributed measure...
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ISBN:
(数字)9781510649569
ISBN:
(纸本)9781510649569;9781510649552
The paper depicts nowadays approach for object-oriented hardware modeling, synthesis, implementation, and management. Implementation is realized for the control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The paper presents a solution described as a software model based on a method of address space management called the Component Internal Interface (CII) and its aftermath: its' updated version Virtual Bus CII (vBUScomp). Therefore, progress and evaluation of these methods and differences between them are described. The article presents the software model implemented as an independent tool for test, maintenance, verification, and development CII based reconfigurable hardware systems.
Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end ite...
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Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.
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