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Implementation of encoder and decoder for low-density parity-check codes in continuous-variable quantum key distribution on a field programmable gate array

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OPTICAL ENGINEERING 2023年第1期62卷 014105-014105页

作者： Sun, Xiunan Liang, Hao Univ Sci & Technol China Sch Cybersci Hefei Peoples R China Univ Sci & Technol China State Key Lab Particle Detect & Elect Hefei Peoples R China Univ Sci & Technol China Dept Modern Phys Hefei Peoples R China

Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, similar to 0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps d

关键词： continuous-variable quantum key distribution quasi-cyclic low-density parity-check offset minimum sum algorithm field programmable gate array

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