The explosive growth of data volume from next generation high-resolution and high-speed hyperspectral remote sensing systems will compete with the limited on-board storage resources and bandwidth available for the tra...
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The explosive growth of data volume from next generation high-resolution and high-speed hyperspectral remote sensing systems will compete with the limited on-board storage resources and bandwidth available for the transmission of data to ground stations making hyperspectral image compression a mission critical and challenging on-board payload data processing task. The Consultative Committee for Space data Systems (CCSDS) has issued recommended standard CCSDS-123.0-B-1 for lossless multispectral and hyperspectral image compression. In this paper, a very high data-rate performance hardware accelerator is presented implementing the CCSDS-123.0-B-1 algorithm as an IP core targeting a space-grade FPGA. For the first time, the introduced architecture based on the principles of C-slow retiming, exploits the inherent task-level parallelism of the algorithm under BIP ordering and implements a reconfigurable fine-grained pipeline in critical feedback loops, achieving high throughput performance. The CCSDS-123.0-B-1 IP core achieves beyond the current state-of-the-art data-rate performance with a maximum throughput of 213 MSamples/s (3.3 Gbps @ 16-bits) using 11 percent of LUTs and 27 percent of BRAMs of the Virtex-5QV FPGA resources for a typical hyperspectral image, leveraging the full throughput of a single SpaceFibre lane. To the best of our knowledge, it is the fastest implementation of CCSDS-123.0-B-1 targeting a space-grade FPGA to date.
The Consultative Committee for Space data Systems (CCSDS) 121.0-B-2 lossless data compression standard defines a lossless adaptive source coding algorithm which is applicable to a wide range of imaging and nonimaging ...
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The Consultative Committee for Space data Systems (CCSDS) 121.0-B-2 lossless data compression standard defines a lossless adaptive source coding algorithm which is applicable to a wide range of imaging and nonimaging data. We introduce a field-programmable gate array (FPGA) implementation of CCSDS 121.0-B-2 as an intellectual property (IP) core with the following features: (a) it is enhanced with a two-dimensional (2-D) second-order predictor making it more suitable for image compression, (b) it is enhanced with near-lossless compression functionality, (c) its parallel, pipelined architecture provides high data-rate performance with a maximum achievable throughput of 205 Msamples/s (3.2 Gbps at 16 bit) when targeting the Xilinx Virtex-5QV FPGA, and (d) it requires very low FPGA resources. When mission requirements impose lossless image compression, the CCSDS 121.0-B-2 IP core provides a very low implementation cost solution. According to European Space Agency PROBA-3 Bridging Phase, the CCSDS 121.0-B-2 IP core will be implemented in a Microsemi RTAX2000 FPGA, hosted in the dataprocessing unit of the Coronagraph Control Box, of the Association of Spacecraft for Polarimetric and Imaging Investigation of the Corona of the Sun Coronagraph System payload. To the best of our knowledge, it is the fastest FPGA implementation of CCSDS 121.0-B-2 to date, also including a 2-D second-order predictor making it more suitable for image compression. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)
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