Hardware Trojan research has become an important research topic in recent time since the increased awareness of hardware security. In this work, we designed a novel counter-type Hardware Trojan based on one-hot code, ...
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ISBN:
(纸本)9781538634493
Hardware Trojan research has become an important research topic in recent time since the increased awareness of hardware security. In this work, we designed a novel counter-type Hardware Trojan based on one-hot code, which has better performance than classic solutions. By improvement in this work, the dynamic power consumption of counter Trojan has reached a decrease of 25%. At the same time, power consumption peak caused by flipping like 0111111 -> 1000000 under binary encoding was avoided. The performance of designed Trojan has been fully tested in the software-hardware co-verification environment, which shows that Trojan implantation did not influence the proper work of background circuit, only did some tricks in the way we need;and the Trojan latent period is controllable by connecting Trojan circuit to different trigger nodes.
This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code f...
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This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.
The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units. To speedup the summation, high compression ratio counters and compressors are necessary. In th...
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The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units. To speedup the summation, high compression ratio counters and compressors are necessary. In this article, we present a novel method of fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting network. The inputs of the counter are asymmetrically divided into two groups and fed into sorting networks to generate reordered sequences, which can be solely represented by one-hot code sequences. Between the reordered sequence and the one-hot code sequence, three special Boolean equations are established, which can significantly simplify the output Boolean expressions of the counter. Using the above method, we construct and further optimize the (7,3) counter that can perform 27.0%, 26.2%, and 52.0% better in maximum than other designs in delay, area-delay product, and power-delay product, respectively. Similarly, the (15,4) counter is constructed, and it achieves approximately 35.3% shorter delay, while it significantly consumes less power and area. The constructed (31,5) counter has approximately 26.7% higher performance with the area increasing instead. When the counters are embedded in a 16 x 16 bit multiplier, the performance of the multiplier in area delay product and power delay product is 31.8% and 32.1% higher than that embedded in other counter designs, respectively. Besides, we also construct exact/approximate (4:2) compressors based on sorting network, and they are 10.2%-37.4% better in the area-delay product and 223%-48.0% better in power-delay product when they are embedded in an 8 x 8 bit approximate multiplier.
As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary im...
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As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.
This paper presents a method for computing inner products based on the distributed arithmetic principles and thermometer codes. The input is represented in the residue domain using thermometer codes while the output i...
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ISBN:
(纸本)9781479961207
This paper presents a method for computing inner products based on the distributed arithmetic principles and thermometer codes. The input is represented in the residue domain using thermometer codes while the output is encoded in the one-hot code format. Compared to the conventional methods of evaluating inner products using binary format, the proposed system provides an elegant way of performing the modular inner products computation due to the absence of the 2(n) modulo operation encountered in binary based methods. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format with no carry propagation involved in the addition.
This project employs an innovative approach to design optimized saturated binary counters, such as (7, 3), (15, 4), and other variants, which rely on sorting networks and 4:2 exact compressors. Compressors and counter...
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