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IEEE International Performance, Computing, and Communications Conference (IPCCC)

作者： Chang, Keyang Du, Yimin Liu, Min Shi, Jinglin Zhou, Yiqing Li, Yongkang Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

ISBN: (纸本)9798350302936

Digital Twin technology is a valuable approach for modeling and simulating complex network systems. It is used to comprehensive analysis of network performance, protocols and configurations. The ns-3 simulator has the capability to simulate real-world network environments, supporting the implementation of Network Digital Twins. However, the current ns-3 simulator pays more attention to simulating network protocol algorithm, while ignoring the network packet processing in device node. It can not simulate packet processing based on OS. In this paper we propose a new architecture based on ns-3 for simulating OS packet processing mechanism, called NS3 - Modular packet processing Simulation Architecture (NS3-MPPSA). In NS3-MPPSA, various hardware resources involved in packet processing are modeled. packet processing mechanisms can be implemented by selecting and combining processing units flexibly. The obtained results indicate that NS3-MPPSA enhances the capabilities of ns-3, enabling accurate and realistic simulation of packet processing. Thus, it provides better support for the implementation of Network Digital Twins.

关键词： NS3-MPPSA packet processing Hardware ns-3 Digital Twin

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Accelerating packet processing in Container Overlay Networks via packet-level Parallelism 37

Accelerating Packet Processing in Container Overlay Networks...

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37th IEEE International Parallel and Distributed processing Symposium (IPDPS)

作者： Lei, Jiaxin Munikar, Manish Lu, Hui Jia, Rao Binghamton Univ Binghamton NY 13902 USA Univ Texas Arlington Arlington TX USA

ISBN: (纸本)9798350337662

Overlay networks serve as the de facto network virtualization technique for providing connectivity among distributed containers. Despite the flexibility in building customized private container networks, overlay networks incur significant performance loss compared to physical networks (i.e., the native). The culprit lies in the inclusion of multiple network processing stages in overlay networks, which prolongs the network processing path and overloads CPU cores. In this paper, we propose MFLOW, a novel packet steering approach to parallelize the in-kernel data path of network flows. MFLOW exploits packet-level parallelism in the kernel network stack by splitting the packets of the same flow into multiple micro-flows, which can be processed in parallel on multiple cores. MFLOW devises new, generic mechanisms for flow splitting while preserving in-order packet delivery with little overhead. Our evaluation with both micro-benchmarks and real-world applications demonstrates the effectiveness of MFLOW, with significantly improved performance - e.g., by 81% in TCP throughput and 139% in UDP compared to vanilla overlay networks. MFLOW even achieved higher TCP throughput than the native (e.g., 29.8 vs. 26.6 Gbps).

关键词： packet processing Kernel Network Stack Container Overlay Networks

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FlexPipe: Fast, Flexible and Scalable packet processing for High-Performance SmartNICs 31

FlexPipe: Fast, Flexible and Scalable Packet Processing for ...

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31st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Zyla, Klajd Liess, Marco Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (纸本)9798350325997

Data centers have been struggling to provide the necessary processing capacity to handle the surging rate of network traffic that is generated in an increasingly connected and service-oriented world. As a result, SmartNICs play an even more important role than before as they can offload various network applications and hence free CPU resources for application-layer processing, increase performance and reduce processing time. However, they often do not support flows with different offload requirements and cannot dynamically allocate offloads in runtime. In order to address these limitations, we propose FlexPipe, a fast, flexible and scalable packet-processing architecture for high-performance SmartNICs. Our design enables low-latency and runtime-reconfigurable packet forwarding at high traffic rates with minimal area overhead. Furthermore, it provides load-aware packet steering toward multiple offload units of the same type for low-bandwidth offloads. We implement a prototype of FlexPipe in Verilog and validate it via cycle-accurate register-transfer level simulations. Our evaluation results show that FlexPipe can process packets of arbitrary size with different offload requirements at line rate and on average 1.9x faster than a SmartNIC with a predefined sequence of offloads and 1.8x faster than PANIC, a flexible state-of-the-art SmartNIC.

关键词： SmartNICs packet processing Load balancing SDN 6G

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packet processing and data plane program verification: A survey with tools, techniques, and challenges

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INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 2023年第14期36卷 e5554-e5554页

作者： Akarte, Harishchandra A. A. Yadav, Dharmendra K. K. Motilal Nehru Natl Inst Technol Allahabad Dept Comp Sci & Engn Allahabad India

In today's era of fast-growing network-enabled devices combined, it increases the complexity of the network. This leads to the massive data packet transfer on the network via the data plane in a software-defined networking environment. The programmable packet processing in a data plane may introduce indirect bugs that are hard to catch manually. To avoid catastrophic after-effects, such programs need to be formally verified. Researchers have proposed various tools and techniques to verify the data plane program using the P4 language. Most of the researchers have used the concept of assertion and symbolic execution to provide P4 verification approaches. As symbolic execution does not scale up well, researchers have proposed different techniques, which include the use of constraints, slicing of the program, parallelization, data plane verification, program verification, and so on. The tools have experimented with different choices for compiler optimization. In this article, we perform a pervasive survey on various verification tools and techniques based on data plane programming using domain-specific language like P4 from the inception of the concept. We have compared the packet processing tools developed as per the requirement of time with their ideology and the impact of change.

关键词： P4 programming packet processing programmable switches software defined networking verification

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Containing Low Tail-Latencies in packet processing Using Lightweight Virtualization 35

Containing Low Tail-Latencies in Packet Processing Using Lig...

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35th International Teletraffic Congress (ITC)

作者： Wiedner, Florian Helm, Max Daichendt, Alexander Andre, Jonas Carle, Georg Tech Univ Munich Dept Comp Engn Garching Germany

ISBN: (纸本)9798350360080;9798350360073

packet processing in current network scenarios faces complex challenges due to the increasing prevalence of requirements such as low latency, high reliability, and resource sharing. Virtualization is a potential solution to mitigate these challenges by enabling resource sharing and on-demand provisioning;however, ensuring high reliability and ultra-low latency remains a key challenge. Since bare-metal systems are often impractical because of high cost and space usage, and virtual machines require substantial additional resources, we evaluate the utilization of containers as a potential lightweight solution for low-latency-enabled packet processing. Herein, we discuss the benefits and drawbacks and encourage the use of container environments in low-latency packet processing when the degree of isolation of customer data is adequate and bare metal systems are unaffordable. Our results demonstrate that containers achieve similar latency performance with more predictable tail-latency behavior compared to bare metal packet processing. Furthermore, we show that the overhead caused by virtualization is negligible in tail latencies.

关键词： low-latency testbed container virtualization packet processing

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Memory Network Architecture for packet processing in Functions Virtualization

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IEEE TRANSACTIONS ON NETWORK AND SERVICE MANAGEMENT 2022年第3期19卷 3304-3322页

作者： Korikawa, Tomohiro Oki, Eiji Kyoto Univ Grad Sch Informat Kyoto 6068501 Japan NTT Corp Network Innovat Ctr Tokyo 1808585 Japan

packet processing tasks in network functions require high-performance memory systems to understand the packet information, update the packet content, and search the databases. While network virtualization is expected to bring flexible and adaptive network with reduced cost by using commercial off-the-shelf (COTS) hardware and programmable data plane technology, network function performance suffers from the poor memory systems in COTS computers and lack of scalability in programmable hardware devices. This paper proposes a memory network architecture for packet processing based on memory-centric, disaggregated computing. Unlike processor-centric architecture in today's COTS computers, the memory network consists of multiple memory devices, where processing for the incoming packets is completed. The proposed architecture reduces packet processing latency by eliminating communication between the processor devices and the memory devices. Also, the proposed architecture provides scalability of hardware resources by dynamic memory device allocation depending on the complexity of the network function, memory-intensiveness of packet processing, and traffic load. The numerical results show that the proposed architecture reduces accumulated latency for memory accesses and increases throughput compared to the conventional, processor-centric architectures, where every memory access requires communication between the processor devices and the memory devices. The proposed architecture also reduces latency and increases throughput by allocating additional memory devices to memory-intensive tasks.

关键词： Memory management Random access memory Computer architecture Task analysis Virtualization Hardware Performance evaluation Network functions virtualization packet processing memory network memory-centric computing disaggregated computing

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HLSCAM: Fine-Tuned HLS-Based Content Addressable Memory Implementation for packet processing on FPGA

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ELECTRONICS 2025年第9期14卷 1765-1765页

作者： Abbasmollaei, Mostafa Ould-Bachir, Tarek Savaria, Yvon Polytech Montreal Dept Comp Engn MOTCE Lab Montreal PQ H3T 1J4 Canada Polytech Montreal Dept Elect Engn Montreal PQ H3T 1J4 Canada

Content Addressable Memories (CAMs) are pivotal in high-speed packet processing systems, enabling rapid data lookup operations essential for applications such as routing, switching, and network security. While traditional Register-Transfer Level (RTL) methodologies have been extensively used to implement CAM architectures on Field-Programmable Gate Arrays (FPGAs), they often involve complex, time-consuming design processes with limited flexibility. In this paper, we propose a novel templated High-Level Synthesis (HLS)-based approach for the design and implementation of CAM architectures such as Binary CAMs (BCAMs) and Ternary CAMs (TCAMs) optimized for data plane packet processing. Our HLS-based methodology leverages the parallel processing capabilities of FPGAs through employing various design parameters and optimization directives while significantly reducing development time and enhancing design portability. This paper also presents architectural design and optimization strategies to offer a fine-tuned CAM solution for networking-related arbitrary use cases. Experimental results demonstrate that HLSCAM achieves a high throughput, reaching up to 31.18 Gbps, 9.04 Gbps, and 33.04 Gbps in the 256x128, 512x36, and 1024x150 CAM sizes, making it a competitive solution for high-speed packet processing on FPGAs.

关键词： Content-Addressable Memory FPGA High-Level Synthesis packet processing

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A packet processing Scheme in 5G MAC Protocol Using DPDK 14

A Packet Processing Scheme in 5G MAC Protocol Using DPDK

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14th International Conference on Information and Communication Technology Convergence, ICTC 2023

作者： Song, Jaesu Chung, Heesang Electronics and Telecommunications Research Institute Mobile Communication Research Division Dae-Jeon Korea Republic of

ISBN: (纸本)9798350313277

In this paper, we propose a packet processing scheme in the MAC protocol of 5G NR. In general, data plane protocols such as MAC, RLC, and PDCP use DPDK library for high-speed data processing. We implement the MAC layer of 5G NR using DPDK library on high performance server platform and measure the packet processing time of the MAC layer. Specifically, the multiplexing and demultiplexing functions of the MAC protocol are implemented and tested on a server platform. Through these measurement results, we found that what affects the packet processing time is the number of MAC SDUs multiplexed into the MAC TB rather than the size of the MAC PDU. We also compare the packet processing time according to the existing packet processing scheme and the newly proposed method applied to 5G NR MAC. Through this, it was confirmed that the new packet processing method shows better performance when a large number of packets are multiplexed into one MAC PDU. © 2023 IEEE.

关键词： 3GPP 5G NR DPDK MAC packet processing

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Survey on Software Solution for High Performance packet processing

Survey on Software Solution for High Performance Packet Proc...

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International Conference on Distributed Computing and Optimization Tech-niques (ICDCOT)

作者： Kishore, Nanda Rajarajeswari, S. Sunagar, Pramod Kanavalli, Anita Ramaiah Inst Technol Comp Sci & Engn Bangalore 560054 India

ISBN: (纸本)9789811922817;9789811922800

With the evolution of the internet, we see a huge spike in the number of network users. The range of generated internet traffic in most of the various locations is increasing rapidly. The latest networking environment should deliver high throughput, high speed, high bandwidth, and fewer delay properties. Else it leads to data loss which is costly in packet processing. This survey contributes to finding a faster software solution to packet processing framework to overcome the challenges faced by traditional networks. This paper aims at packet acquisition and distribution methods based on packet processing models such as Data Plane Development Kit (DPDK), Netmap, Netslice, and PF-RING. And come up with a model which can productively decrease packet loss, successively enhance the performance rate and reduce resource waste. Comparison between the packet processing frameworks depicts that DPDK based data processing has dominance over Netmap, Netslice, and PF-RING in packet processing.

关键词： packet processing DPDK Netslice Netmap Pf_ring

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An Improved 30 Gbps-Class Large-Capacity packet processing Method Using Core Isolation Technology

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Journal of Mobile Multimedia 2022年第6期18卷 1497-1512页

作者： Kwon, Youngsun Son, Moonhee Chang, Hoon Dept. of Computer Science and Engineering Soongsil University South Korea Dept. of Technical Research Center Entobilsoft Inc. South Korea

With the spread of 5G services and the development of IoT technology, network traffic for information delivery is increasing in capacity. As network traffic increases, cyber threats also increase, resulting in an increasing importance on traffic analysis. The existing packet processing engine generates a signature by analyzing the characteristics of the attack after the occurrence of suspicious traffic, and based on this, it is difficult to properly respond to new and variant attack traffic because a manual response method is performed to detect the same attack. In addition, even during a network operation, only analysis results generated by passive filtering appear, and when abnormal or suspicious traffic is observed, the quality of the report is often affected by the analysis capability of the administrator. The packet processing method proposed in this paper applies the core isolation method to the NUMA structure applied to the existing 20 Gbps packet processing engine to increase the accessibility of the existing NUMA memory structure and lower the packet drop rate to enable high-capacity 30 Gbps traffic processing. Using the proposed processing engine, it is possible to determine the degree of possibility of abnormal traffic, preferentially by a quick analysis of suspicious traffic rather than a detailed analysis of traffic. © 2022 River Publishers. All rights reserved.

关键词： core isolation huge page. Network packet processing traffic analysis

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