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IEEE International Conference on Big Knowledge (ICBK)

作者： Wen Qin Xin Luo School of Computer Science and Technology Chongqing University of Posts and Telecommunications Chongqing China Chongqing Institute of Green and Intelligent Technology Chinese Academy of Sciences Chongqing School University of Chinese Academy of Sciences Chongqing China College of Computer and Information Science Southwest University Chongqing China

A latent feature analysis (LFA) model is highly efficient in performing representation learning to high-dimensional incomplete (HDI) data like user-item interactions data from a recommender system. Stochastic gradient descent (SGD) is frequently adopted as the learning algorithm by an LFA model owing to its low computational complexity. However, a standard SGD algorithm is in nature a serial algorithm, which affects the resultant LFA model's scalability on mass HDI data. On the other hand, existing parallel SGD algorithms commonly suffer from low speedup when building an LFA model due to their frequent synchronizations during the training process. Motivated by this discovery, this paper proposes an Asynchronously Alternative Stochastic Gradient Descent (A 2 SGD) algorithm to achieve an efficiently parallelized LFA model on shared-memory with two fold-ideas: a) adopting the principle of an alternative stochastic gradient descent algorithm to decouple the LFA process, thereby achieving two parallelizable subtasks with minimal learning information loss; b) designing a novel parallelization scheme by eliminating synchronizations from both the subtask and the thread perspectives, i.e., both sub-tasks are taken simultaneously, and their affiliated threads also executes without synchronizations. Rigorously theoretical convergence proof illustrates that the newly-proposed parallelization scheme guarantees the convergence of a resultant LFA model. Detailed experimental results on four real HDI datasets indicate that an A 2 SGD-based LFA model outperforms several state-of-the-art parallel SGD-based LFA models in terms of both missing data estimation accuracy and parallelization speedup.

关键词： Training Representation learning Computational modeling Scalability Stochastic processes Data models parallel algorithms

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An Efficient parallel Implementation of a Perfect Hashing Method for Hypergraphs

An Efficient Parallel Implementation of a Perfect Hashing Me...

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IEEE International Symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Somesh Singh Bora Uç ar INRIA and LIP (CNRS - Universit&#x00E9 de Lyon - INRIA - ENS Lyon) France

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Querying the existence of an edge in a given graph or hypergraph is a building block in several algorithms. Hashing-based methods can be used for this purpose, where the given edges are stored in a hash table in a preprocessing step, and then the queries are answered using the lookup operations. While the general hashing methods have fast lookup times in the average case, the worst case run time is much higher. Perfect hashing methods take advantage of the fact that the items to be stored are all available and construct a collision free hash function for the given input, resulting in an optimal lookup time even in the worst case. We investigate an efficient shared-memory parallel implementation of a recently proposed perfect hashing method for hypergraphs. We experimentally compare the resulting parallel algorithms with the state-of-the-art and demonstrate better run time and scalability on a set of hypergraphs corresponding to real-life sparse tensors.

关键词： Hash functions Distributed processing Tensors Scalability Conferences Sparse matrices parallel algorithms

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Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM 21

Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM

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50th International Conference on parallel Processing (ICPP)

作者： Ghanim, Fady Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450384414

The parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the underlying memory access mode used, the most powerful of which is the Concurrent Read Concurrent Write (CRCW) model. A PRAM algorithm describes a series of rounds, each of which consists of a collection of operations that can be executed concurrently within the same time step. However, the lack of support for concurrent memory accesses and the prevalence of asynchronous programming models led to the belief that implementing CRCW PRAM algorithms is unattainable and prompted many to avoid this model except for theoretical studies of optimal performance. In this work, we study the arbitrary and common concurrent writes in the CRCW PRAM model and explore implementation challenges on general-purpose systems. Moreover, we examine current practices for implementing common/arbitrary concurrent writes and propose a new efficient lightweight and thread-safe method to implement concurrent writes through leveraging atomic instructions. To demonstrate the efficacy of our method, we developed OpenMP kernels for classical CRCW PRAM algorithms and provide experimental results and comparisons based on run time performance measured over the x86 multicore architecture. Our results show a performance speedup compared to current practices up to 4.5x across all our benchmarks.

关键词： CRCW PRAM parallel algorithms Arbitrary Concurrent Writes Write-conflict resolution parallel Architectures

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parallel algorithms for 2-D cylindrical transport equations of eigenvalue problem

Parallel algorithms for 2-D cylindrical transport equations ...

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International Conference on Mathematics and Computational Methods Applied to Nuclear Science and Engineering, M and C 2013

作者： Wei, Junxia Yang, Shulin Institute of Applied Physics and Computational Mathematics No. 2 Fenhao Donglu Haidian District Beijng China

ISBN: (纸本)9781627486439

In this paper, aimed at the neutron transport equations of eigenvalue problem under 2-D cylindrical geometry on unstructured grid, the discrete scheme of Sn discrete ordinate and discontinuous finite is built, and the parallel computation for the scheme is realized on MPI systems. Numerical experiments indicate that the designed parallel algorithm can reach perfect speedup, it has good practicality and scalability.

关键词： parallel algorithms

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Performance Evaluation and Improvement of Real-Time Computer Vision Applications for Edge Computing Devices 21

Performance Evaluation and Improvement of Real-Time Computer...

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ACM/SPEC International Conference on Performance Engineering (ICPE)

作者： Gutierrez, Julian Agostini, Nicolas Bohm Kaeli, David Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781450383318

Advances in deep neural networks have provided a significant improvement in accuracy and speed across a large range of Computer Vision (CV) applications. However, our ability to perform real-time CV on edge devices is severely restricted by their limited computing capabilities. In this paper we employ Vega, a parallel graph-based framework, to study the performance limitations of four heterogeneous edge-computing platforms, while running 12 popular deep learning CV applications. We expand the framework's capabilities, introducing two new performance enhancements: 1) an adaptive stage instance controller (ASI-C) that can improve performance by dynamically selecting the number of instances for a given stage of the pipeline;and 2) an adaptive input resolution controller (AIR-C) to improve responsiveness and enable real-time performance. These two solutions are integrated together to provide a robust real-time solution. Our experimental results show that ASI-C improves run-time performance by 1.4x on average across all heterogeneous platforms, achieving a maximum speedup of 4.3x while running face detection executed on a high-end edge device. We demonstrate that our integrated optimization framework improves performance of applications and is robust to changing execution patterns.

关键词： pipeline framework heterogeneous systems parallel algorithms run-time performance management SoC machine learning

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Supercomputer-Based Simulation of the Hydrodynamics of River Mouth Areas 15th

Supercomputer-Based Simulation of the Hydrodynamics of River...

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15th International Scientific Conference on parallel Computational Technologies (PCT)

作者： Sukhinov, Alexander, I Chistyakov, Alexander E. Nikitina, Alla, V Kuznetsova, Inna Yu Atayan, Asya M. Protsenko, Elena A. Litvinov, Vladimir N. Don State Tech Univ Rostov Na Donu Russia Southern Fed Univ Rostov Na Donu Russia Supercomp & Neurocomp Res Ctr Taganrog Russia AP Chekhov Univ Taganrog Taganrog Russia Don State Agr Univ Azov Black Sea Engn Inst Zernograd Russia

ISBN: (纸本)9783030816919;9783030816902

The article is devoted to the development and numerical implementation of a 3D hydrodynamic mathematical model intended for computing the movement velocity of the aquatic environment in river mouth areas. The equations in the hydrodynamic model of a shallow reservoir are approximated using the balance method and taking into account the fullness of control areas. This approach makes it possible to take into account the complex geometry of the coastline and the bottom and significantly increase the accuracy of computations. The numerical methods and algorithms we have developed are the basis of the software package that we tested on a supercomputer cluster using MPI technology. The package can simulate hydrodynamic processes that take place in shallow-water bodies. It is designed for computing systems with distributed memory. To test the functionality of the software package, we use the mathematical model to compute the rise in the water level of a river and its course in the mouth area. The geometry of the computational area is given in the form of a depth map. The computations for a rectangular grid with 1000 x 1000 x 60 nodes on 24 processors yield an acceleration by more than a factor of 15.

关键词： Mathematical modeling 3D models Hydrodynamics River mouth area Splitting schemes for physical processes parallel algorithms

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IExchange: Asynchronous Communication and Termination Detection for Iterative algorithms 11

IExchange: Asynchronous Communication and Termination Detect...

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IEEE 11th Symposium on Large Data Analysis and Visualization (LDAV)

作者： Morozov, Dmitriy Peterka, Tom Guo, Hanqi Raj, Mukund Xu, Jiayi Shen, Han-Wei Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Argonne Natl Lab Lemont IL USA Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781665432832

Iterative parallel algorithms can be implemented by synchronizing after each round. This bulk-synchronous parallel (BSP) pattern is inefficient when strict synchronization is not required: global synchronization is costly at scale and prohibits amortizing load imbalance over the entire execution, and termination detection is challenging with irregular data-dependent communication. We present an asynchronous communication protocol that efficiently interleaves communication with computation. The protocol includes global termination detection without obstructing computation and communication between nodes. The user's computational primitive only needs to indicate when local work is done;our algorithm detects when all processors reach this state. We do not assume that global work decreases monotonically, allowing processors to create new work. We illustrate the utility of our solution through experiments, including two large data analysis and visualization codes: parallel particle advection and distributed union-find. Our asynchronous algorithm is several times faster with better strong scaling efficiency than the synchronous approach.

关键词： Computing methodologies parallel computing methodologies parallel algorithms Massively parallel algorithms

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A Deterministic Algorithm for the MST Problem in Constant Rounds of Congested Clique 2021

A Deterministic Algorithm for the MST Problem in Constant Ro...

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53rd Annual ACM SIGACT Symposium on Theory of Computing (STOC)

作者： Nowicki, Krzysztof Univ Copenhagen Copenhagen Denmark Univ Wroclaw Wroclaw Poland

ISBN: (纸本)9781450380539

In this paper we show that the Minimum Spanning Tree problem (MST) can be solved deterministically in O(1) rounds of the Congested Clique model. In the Congested Clique model there are n players that perform computation in synchronous rounds. Each round consist of a phase of local computation and a phase of communication, in which each pair of players is allowed to exchange O(log n) bit messages. The studies of this model began with the MST problem: in the paper by Lotker, Pavlov, Patt-Shamir, and Peleg [SPAA'03, SICOMP'05] that defines the Congested Clique model the authors give a deterministic O(log log n) round algorithm that improved over a trivial O(log n) round adaptation of Boravka's algorithm. There was a sequence of gradual improvements to this result: an O(log log log n) round algorithm by Hegeman, Pandurangan, Pemmaraju, Sardeshmukh, and Scquizzato [PODC'15], an O(log* n) round algorithm by Ghaffari and Parter, [PODC'16] and an O(1) round algorithm by Jurdzinski and Nowicki, [SODA'18], but all those algorithms were randomized. Therefore, the question about the existence of any deterministic o(log log n) round algorithms for the Minimum Spanning Tree problem remains open since the seminal paper by Lotker, Pavlov, Patt-Shamir, and Peleg [SPAA'03, SICOMP'05]. Our result resolves this question and establishes that O(1) rounds is enough to solve the MST problem in the Congested CI iq ue model, even if we are not allowed to use any randomness. Furthermore, the amount of communication needed by the algorithm makes it applicable to a variant of the M PC model using machines with local memory of size O(n).

关键词： Minimum Spanning Tree MST Deterministic algorithms Graph algorithms Distributed algorithms Congested Clique parallel algorithms Massively parallel algorithms MapReduce

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Multi-Threaded control of NAND Flash memory array 18

Multi-Threaded control of NAND Flash memory array

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IEEE Workshop on Microelectronics and Electron Devices (WMED)

作者： Nubile, Luca De Santis, Luca Cardinali, Riccardo Micron Semicond Italy Avezzano Italy

ISBN: (纸本)9781728162744

Flash memory devices operations like read, program and erase are performed by sequences called "algorithms". An algorithm is mainly composed of phases where accurate voltages are computed and applied to the array cells and phases where data are moved through different latches in data buffers. The fast-increasing complexity of multi-bit NAND memory algorithms made it natural to realize control logic on a microprocessor, in the form of firmware routines. The HW/FW co-design enables a safer complexity management, allows development of algorithms in parallel with physical design and allows acceleration of development time to fit aggressive time-to-market requirements. Again, to follow the increasingly performance requirements different kind of multi-thread microprocessor solutions have been proposed in the years to get the best performance-power-area (PPA) trade-off. This article proposes one possible approach to performance optimization by a multi-threaded approach, without an immediate downside for area and power. The most innovative point of the new architecture is the deep adherence between intrinsic paralleliz able physical processes inside a NAND Flash and the number of threads, busses and physical executors. As shown, this solution introduces tangible advantages in terms of performance.

关键词： Flash memories Integrated Circuit design Multitasking parallel algorithms Multi-Threading

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Energy cost evaluation of parallel algorithms for multiprocessor systems

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CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS 2013年第1期16卷 77-90页

作者： Wang, Zhuowei Xu, Xianbin Xiong, Naixue Yang, Laurence T. Zhao, Wuqing Wuhan Univ Sch Comp Wuhan 430000 Peoples R China Georgia State Univ Dept Comp Sci Atlanta GA 30303 USA St Francis Xavier Univ Dept Comp Sci Antigonish NS B2G 1C0 Canada

With the continuous development of hardware and software, Graphics Processor Units (GPUs) have been used in the general-purpose computation field. They have emerged as a computational accelerator that dramatically reduces the application execution time with CPUs. To achieve high computing performance, a GPU typically includes hundreds of computing units. The high density of computing resource on a chip brings in high power consumption. Therefore power consumption has become one of the most important problems for the development of GPUs. This paper analyzes the energy consumption of parallel algorithms executed in GPUs and provides a method to evaluate the energy scalability for parallel algorithms. Then the parallel prefix sum is analyzed to illustrate the method for the energy conservation, and the energy scalability is experimentally evaluated using Sparse Matrix-Vector Multiply (SpMV). The results show that the optimal number of blocks, memory choice and task scheduling are the important keys to balance the performance and the energy consumption of GPUs.

关键词： GPUs parallel algorithms Energy scalability Energy conservation Performance

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