Given a Cartesian product G = G(1) x ... x G(M) (m greater than or equal to 2) of nontrivial connected graphs G(i) and the base d, dimension D de Bruijn graph B(d, D), it is investigated under which conditions G is (o...
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Given a Cartesian product G = G(1) x ... x G(M) (m greater than or equal to 2) of nontrivial connected graphs G(i) and the base d, dimension D de Bruijn graph B(d, D), it is investigated under which conditions G is (or is not) a subgraph of B(d,D). We present a complete solution of this problem for the case D greater than or equal to 4. For D = 3, we give partial results including a complete solution for the case that G is a torus, i.e., G is the Cartesian product of cycles.
In this paper we present an approach to parallelization of the program for computation of axisymmetrical forging process. The parallel algorithm we have applied is based on non-overlapping domain decomposition method....
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In this paper we present an approach to parallelization of the program for computation of axisymmetrical forging process. The parallel algorithm we have applied is based on non-overlapping domain decomposition method. A mesh of elements is divided into layers assigned to different processes. The parallel program was written in C using PVM and it was implemented on Convex Exemplar SPP1000 and on networked workstations IBM RS/6000-320. We have investigated dependence of performance of the elaborated parallel program on number of process and on number of nodes in the mesh.
The realization of truly heterogeneous database systems is hampered by two principal obstacles. One is the unsuitability of traditional transaction models;this has led to the proposal of a number of new, advanced tran...
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A systematic method of mapping algorithms from single assignment algorithms into systolic arrays is presented. The method is based on a space-time mapping technique of the index sets. We present a method of generation...
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ISBN:
(纸本)0780320182
A systematic method of mapping algorithms from single assignment algorithms into systolic arrays is presented. The method is based on a space-time mapping technique of the index sets. We present a method of generation and selection of a valid transform dependency matrix that will yield an optimal or near optimal systolic array once it is mapped. The proposed method increases the visibility of the architecture in terms of processor delay and communication between processors at the algorithmic level, so that the designer is able to select a desired array at early stages of the design. An example of the proposed method is given.
In this work, a parallel scheduling algorithm for scheduling a set of n partially ordered tasks on an m-processor parallelcomputing system is studied. The method is based on a conventional list scheduling, in particu...
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