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parallel circuit simulation ON SUPERCOMPUTERS

PROCEEDINGS OF THE IEEE 1989年第12期77卷 1915-1931页

作者： SALEH, RA GALLIVAN, KA CHANG, MC HAJJ, IN SMART, D TRICK, TN TEXAS INSTRUMENTS INC CTR SEMICOND PROC DESIGN DALLAS TX 75265 USA UNIV ILLINOIS COORDINATED SCI LAB URBANA IL 61801 USA ANALOG DEVICES INC DIV SEMICOND WILMINGTON MA 01887 USA

circuit simulation is a very time-consuming and numerically intensive application, especially when the problem size is large as in the case of VLSI circuits. To improve the performance of circuit simulators without sacrificing accuracy, a variety of parallel processing algorithms have been investigated. Research in the field of parallel circuit simulation is surveyed, and the ongoing research in this area at the University of Illinois is described. Both standard and relaxation-based approaches are considered. In particular, the forms of parallelism available within the direct method approach, used in programs such as SPICE2 and SLATE, and within the relaxation-based approaches, such as waveform relaxation, iterated timing analysis, and waveform-relaxation-Newton, are described. The specific implementation issues addressed are primarily related to general-purpose multiprocessors with a shared-memory architecture having a limited number of processors, although many of the comments apply to a number of other architectures

关键词： SLATE SPICE2 VLSI VLSI circuits circuit analysis computing general-purpose multiprocessors iterated timing analysis iterative methods numerically intensive application parallel circuit simulation parallel processing parallel processing algorithms relaxation theory relaxation-based shared-memory architecture waveform relaxation waveform-relaxation-Newton

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parallel circuit simulation on Multi/Many-core Systems

Parallel Circuit Simulation on Multi/Many-core Systems

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26th IEEE International parallel and Distributed Processing Symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Chen, Xiaoming Wang, Yu Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9780769546766

SPICE is widely used for transistor-level circuit simulation. However, with the growing complexity of the VLSI at nano-scale, the traditional SPICE simulator has become inefficient to provide accurate verifications. This thesis tries to accelerate transistor-level simulation on multi/many-core systems, and we will solve 3 problems: 1) develop a parallel sparse LU factorization algorithm for circuit simulation;2) implement the matrix solver on GPU to further accelerate the solver;3) develop a circuit partitioning based parallel simulation approach on distributed machines to obtain better scalability. The experimental results show that the proposed parallel LU factorization algorithm effectively accelerates the matrix solver for circuit simulation on both CPU and GPU.

关键词： parallel circuit simulation parallel LU Factorization GPU Acceleration

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A parallel BBD MATRIX SOLUTION FOR MIMD parallel circuit simulation

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1995年第1期E78A卷 88-93页

作者： KAGE, T NIITSUMA, J Fujitsu Lab Ltd Atsugi Japan

We developed a parallel bordered-block-diagonal (BBD) matrix solution for parallel circuit simulation. In parallel circuit simulation on a MIMD parallel computer, a circuit is partitioned into as many subcircuits as the processors of a parallel computer. circuit partition produce a BBD matrix. In parallel BBD matrix solution, diagonal blocks are easily solved separately in each processor. It is difficult, however, to solve the interconnection (IC) submatrix of a BBD matrix effectively in parallel. To make matters worse, the more a circuit is partitioned into subcircuits for highly parallel circuit simulation, the larger the size of an IC submatrix becomes. From an examination, we found that an IC submatrix is more dense (about 30% of all entries are non-zeros) than a normal circuit matrix, and the non-zeros per row in an IC submatrix are almost constant with the number of subcircuits. To attain high-speed circuit simulation, we devised a data structure for BBD matrix processing and an approach to parallel BBD matrix solution. Our approach solves the IC submatrix in a BBD matrix as well as the diagonal blocks in parallel using all processors. In this approach, we allocate an IC submatrix in block-wise order rather than in dot-wise order onto all processors. Thus, we balance the processor performance with the communication capacity of a parallel computer system. When we changed the block size of IC submatrix allocation from dot-wise order to 8 x 8 block-wise order, the 8 x 8 block-wise order allocation almost halved the matrix solution time. The parallel simulation of a sample circuit with 3277 transistors was 16.6 times faster than a single processor when we used 49 processors.

关键词： parallel circuit simulation MIMD parallel COMPUTER circuit PARTITIONING BORDERED-BLOCK-DIAGONAL (BBD) MATRIX LU-DECOMPOSITION

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A circuit PARTITIONING APPROACH FOR parallel circuit simulation

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第3期E77A卷 461-466页

作者： KAGE, T KAWAFUJI, F NIITSUMA, J Fujitsu Lab Ltd Atsugi-shi Japan

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps: Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ..., 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

关键词： circuit PARTITIONING parallel circuit simulation SUBcircuitS INTERCONNECTION NODES BORDERED-BLOCK-DIAGONAL (BBD) MATRIX

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NICSLU: An Adaptive Sparse Matrix Solver for parallel circuit simulation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuitS AND SYSTEMS 2013年第2期32卷 261-274页

作者： Chen, Xiaoming Wang, Yu Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

The sparse matrix solver has become a bottleneck in simulation program with integrated circuit emphasis (SPICE)-like circuit simulators. It is difficult to parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of circuit matrices. This paper proposes an adaptive sparse matrix solver called NICSLU, which uses a multithreaded parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate circuit simulation. The solver can be used in all the SPICE-like circuit simulators. A simple method is proposed to predict whether a matrix is suitable for parallel factorization, such that each matrix can achieve optimal performance. The experimental results on 35 matrices reveal that NICSLU achieves speedups of 2.08x similar to 8.57x (on the geometric mean), compared with KLU, with 1 similar to 12 threads, for the matrices which are suitable for the parallel algorithm. NICSLU can be downloaded from http://***.

关键词： parallel circuit simulation parallel LU factorization

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On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level simulation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuitS AND SYSTEMS 2010年第9期29卷 1368-1380页

作者： Meraji, Sina Zhang, Wei Tropper, Carl McGill Univ Sch Comp Sci Montreal PQ H3V 1B9 Canada Natl Univ Def Technol Sch Comp Sci Changsha Hunan Peoples R China

As proscribed by Moore's law, the size of integrated circuits has grown geometrically, resulting in simulation becoming the major bottleneck in the circuit design process. parallel simulation provides us with a way to cope with this growth. In this paper, we describe an optimistic (time warp) parallel discrete event simulator which can simulate all synthesizeable Verilog circuits. We investigate its scalability and describe a machine learning based dynamic load balancing algorithm for use with the simulator. We initially developed two dynamic load balancing algorithms to balance the load and the communication, respectively, during the course of a simulation. Making use of reinforcement learning (RL), we then created an algorithm which is an amalgam of these two algorithms. To the best of our knowledge, this is the first time that RL has been used for the dynamic load-balancing of time warp. We investigated the scalability and the effectiveness of the dynamic load balancing algorithms on gate level simulations of several realistic very large scale integration (VLSI) circuits. Our experimental results showed that our simulator is indeed scalable. They also reveled a 88.6% improvement in the simulation time through the use of our RL algorithm.

关键词： Dynamic load-balancing parallel circuit simulation reinforcement learning (RL) time warp verilog

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