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parallel EVALUATION OF ATTRIBUTE GRAMMARS

IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1992年第2期3卷 206-220页

作者： KLAIBER, A GOKHALE, M SUPERCOMP RES CTR BOWIE MD 20715 USA

This paper examines the generation of parallel evaluators for attribute grammars, targeted to shared-memory MIMD computers. Evaluation-time overhead due to process scheduling and synchronization is reduced by detecting coarse-grain parallelism (as opposed to the naive one-process-per-node approach.) As a means to more clearly expose inherent parallelism, we show how to automatically transform productions of the form X --> YX into list-productions of the form X --> Y+. This transformation allows for many simplifications to be applied to the semantic rules, which can expose a significant degree of inherent parallelism, and thus further increase the evaluator's performance. Effectively, this constitutes an extension of the concept of attribute grammars to the level of abstract syntax.

关键词： ATTRIBUTE GRAMMARS FINE-GRAIN parallelISM MIMD MULTIPROCESSORS parallel compilers parallel PROGRAMMING RESTRUCTURING compilers TASK PARTITIONING

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Trasgo: a nested-parallel programming system

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JOURNAL OF SUPERCOMPUTING 2011年第2期58卷 226-234页

作者： Gonzalez-Escribano, Arturo Llanos, Diego R. Univ Valladolid Dept Informat Valladolid Spain

Programming models of pure nested-parallelism are appealing due to their ease of programming and good analysis and debugging properties. Although their simple synchronization structure is appropriate to represent abstract parallel algorithms, it does not take into account many implementation issues. In this work we present Trasgo, a programming system based on high-level, nested-parallel specifications. We show how it allows to easily express complex combinations of data and task parallelism with a common scheme, hiding the layout and scheduling details. The approach allows the development of a modular compiler where automatic transformation techniques may exploit lower level and more complex synchronization structures, unlocking the limitations of pure nested-parallel programming. This article presents an overview of the features of Trasgo, and its architecture. We present some performance results using well-known parallel algorithms, and a roadmap of improvements and new features to be added to Trasgo.

关键词： High-level programming models parallel compilers

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Optimal uniformization for non-uniform two-level loops using a hybrid method

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JOURNAL OF SUPERCOMPUTING 2023年第11期79卷 12791-12814页

作者： Mahjoub, Shabnam Golsorkhtabaramiri, Mehdi Amiri, Seyed Sadegh Salehi Islamic Azad Univ Dept Comp Engn Langarud Branch Langarud Iran Islamic Azad Univ Dept Comp Engn Babol Branch Babol Iran Islamic Azad Univ Dept Math Babol Branch Babol Iran

The present study proposes a novel method based on evolutionary and fuzzy approaches for unifying two-level perfect nested loops. In this method, the Shuffled Frog Leaping Algorithm (SFLA) is used for achieving optimal answers, and simultaneously, three critical factors are applied as an input in determining basic dependence vectors. The use of fuzzy logic versus fixed coefficients for these three factors has led to the creation of optimal results with high variability and has solved the problem regarding the existence of the main vectors. In addition, the present algorithm has been proposed for many input data so that it can be used in parallel compilers automatically and with low complexity. After implementing and evaluating the proposed method, it was found that, compared to other existing methods, the results achieved were very close to optimal, in the least time, and with the lowest Dependence Cone Size (DCS) and highest number of input vectors.

关键词： Fuzzy Loop transformation parallel compilers SFLA Two-level loops Uniformization

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AUTOMATIC DATA ALLOCATION TO MINIMIZE COMMUNICATION ON SIMD-MACHINES

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JOURNAL OF SUPERCOMPUTING 1993年第4期7卷 387-415页

作者： KNOBE, K NATARAJAN, V MOTOROLA CAMBRIDGE RES CTR CAMBRIDGEMA 02139

Straightforward compilation of array operations onto massively parallel SIMD machines results in a significant amount of interprocessor data motion. Careful allocation of data across the processors eliminates much of this interprocessor data motion. Researchers are working on extending programming languages to include user directives for specifying good data allocation. Our focus is to automate the data allocation through compiler techniques to achieve portability without sacrificing efficiency. These techniques can be used to fully automate the data allocation process or can be integrated with alignment directives. We present here a complete compiler algorithm for the automatic layout of data to minimize interprocessor data motion. Arrays are aligned by mapping them onto the processors based on their usage. Arrays may be mapped differently in different sections of the program, eliminating much of the interprocessor data motion resulting from a static mapping of arrays. We describe an integrated technique for determining the alignment of arrays locally within regions of the program and minimizing communication globally among these regions. This technique starts with the alignments specified by the directives, if any, and determines the alignment for the remaining arrays. The algorithms proposed in this paper were used in the SIMD compilers at Compass, Inc. Preliminary results from the initial implementation of the data optimization techniques described here suggest a significant decrease of the interprocessor data motion. More analysis is required to better understand the range of expected gains and the conditions under which those gains are achieved.

关键词： COMMUNICATION DATA ALIGNMENT DATA ALLOCATION DATA DISTRIBUTION DISTRIBUTED MEMORY parallel compilers SIMD

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A New Combination Method for Improving parallelism in Two and Three Level Perfect Nested Loops

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IEEE ACCESS 2022年 10卷 74542-74554页

作者： Mahjoub, Shabnam Golsorkhtabaramiri, Mehdi Amiri, Seyed Sadegh Salehi Hosseinzadeh, Mehdi Mosavi, Amir Islamic Azad Univ Babol Branch Dept Comp Engn Babol Iran Islamic Azad Univ Babol Branch Dept Math Babol Iran Iran Univ Med Sci Psychosocial Hlth Res Inst Mental Hlth Res Ctr Tehran Iran Univ Human Dev Dept Comp Sci Sulaymaniyah Iraq Obuda Univ John Von Neumann Fac Informat H-1034 Budapest Hungary Univ Publ Serv Inst Informat Soc H-1083 Budapest Hungary Slovak Univ Technol Bratislava Inst Informat Engn Automat & Math Bratislava 81107 Slovakia

The growth of software techniques for implementing applications must go hand in hand with the growth of computer system hardware in the design of multi-core and multi-processor systems;otherwise, we cannot expect to be able to use maximum hardware capacities. One of the most important and challenging techniques for running applications is to run them in parallel with a focus on loop parallelism to reduce execution time. On the other hand, in recent years, many algorithms have been working on volumetric data, i.e., three-dimensional spaces;therefore, parallelization must be possible for all types of two-dimensional and three-dimensional loops. Uniformization is an important part of loop parallelism, and also the present paper's focus. The proposed algorithm in the present paper performed uniformization with a combination of the frog leaping algorithm and the fuzzy system for two- and three-dimensional loops on a wide range of input dependence vectors and achieved a considerable variety of results in the desired time. The results of this study can be used to facilitate the development of parallel codes.

关键词： parallel processing Codes Program processors Runtime Task analysis Pluto Hardware Frog leaping algorithm artificial intelligence parallelization loops uniformization parallel compilers

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Finding performance bugs with the TNO HPF benchmark suite

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2002年第8-9期14卷 691-712页

作者： Denissen, W Sips, HJ Delft Univ Technol Delft Netherlands TPD TNO Delft Netherlands

High-Performance Fortran (HPF) has been designed to provide portable performance on distributed memory machines. An important aspect of portable performance is the behavior of the available HPF compilers. Ideally, a programmer may expect comparable performance between different HPF compilers, given the same program and the same machine. To test the performance portability between compilers, we have designed a special benchmark suite, called the TNO HPF benchmark suite. It consists of a set of HPF programs that test various aspects of efficient parallel code generation. The benchmark suite consists of a number of template programs that are used to generate test programs with different array sizes, alignments, distributions, and iteration spaces. It ranges from very simple assignments to more complex assignments such as triangular iteration spaces, convex iteration spaces, coupled subscripts, and indirection arrays. We have run the TNO HPF benchmark suite on three compilers: the PREPARE prototype compiler, the PGI-HPF compiler, and the GMD Adaptor HPF compiler. Results show performance differences that can be quite large (up to two orders of magnitude for the same test program). Closer inspection reveals that the origin of most of the differences in performance is due to differences in local enumeration and storage of distributed array elements. Copyright (C) 2002 John Wiley Sons, Ltd.

关键词： HPF parallel compilers benchmarking compiler optimizations

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On the parallel execution time of tiled loops

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2003年第3期14卷 307-321页

作者： Högstedt, K Carter, L Ferrante, J AT&T Labs Res Florham Pk NJ 07932 USA Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

Many computationally-intensive programs, such as those for differential equations, spatial interpolation, and dynamic programming, spend a large portion of their execution time in multiply-nested loops that have a regular stencil of data dependences. Tiling is a well-known compiler optimization that improves performance on such loops, particularly for computers with a multileveled hierarchy of parallelism and memory. Most previous work on tiling is limited in at least one of the following ways: they only handle nested loops of depth two, orthogonal tiling, or rectangular tiles. In our work, we tile loop nests of arbitrary depth using polyhedral tiles. We derive a prediction formula for the execution time of such tiled loops, which can be used by a compiler to automatically determine the tiling parameters that minimizes the execution time. We also explain the notion of rise, a measure of the relationship between the shape of the tiles and the shape of the iteration space generated by the loop nest. The rise is a powerful tool in predicting the execution time of a tiled loop. It allows us to reason about how the tiling affects the length of the longest path of dependent tiles, which is a measure of the execution time of a tiling. We use a model of the tiled iteration space that allows us to determine the length of the longest path of dependent tiles using linear programming. Using the rise, we derive a simple formula for the length of the longest path of dependent tiles in rectilinear iteration spaces, a subclass of the convex iteration spaces, and show how to choose the optimal tile shape.

关键词： tiling blocking compiler optimization parallel compilers

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The extension of the I test

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parallel COMPUTING 1998年第14期24卷 2101-2127页

作者： Chang, WL Chu, CP Natl Cheng Kung Univ Inst Informat Engn Tainan 701 Taiwan

The I test is an efficient and precise data dependence method to ascertain whether integer solutions exist for one-dimensional arrays with constant bounds. For one-dimensional arrays with variable limits, the I test assumes that there may exist integer solutions. In this paper, we extend the I test. The extended I test can be applied towards determining whether integer solutions exist for one-dimensional arrays with variable limits, improving the applicable range of the I test. Experiments with benchmark cited from EISPACK, LINPACK, parallel loops, etc. showed that among 1189 pairs of one-dimensional arrays tested, 183 had their data dependence analysis amended by the extended I test. That is, the extended I test increases the success rate of the I test by approximately 15.4%. Comparing with the Power test and the Omega test, the extended I test has higher accuracy than the Power test and shares the same accuracy with the Omega test for these 1189 pairs of arrays, but has much better efficiency over these two well-known tests. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： parallel compilers vector compilers data dependence analysis

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LOOP-LEVEL parallelISM IN NUMERIC AND SYMBOLIC PROGRAMS

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1993年第7期4卷 812-826页

作者： LARUS, JR Computer Sciences Department University of Wisconsin Madison Madison WI USA

This paper describes a new technique for estimating and understanding the speed improvement that can result from executing a program on a parallel computer. The technique requires no additional programming and minimal effort by a program's author. The analysis begins by tracing a sequential program. A parallelism analyzer (pp) uses information from the trace to simulate parallel execution of the program. In addition to predicting parallel performance, pp measures many aspects of a program's dynamic behavior. This paper presents measurements of six substantial programs. These results indicate that the three symbolic (nonnumeric) programs differ substantially from the numeric programs and, as a consequence, cannot be automatically parallelized with the same compilation techniques.

关键词： parallel compilers parallel PROGRAMMING PERFORMANCE PROGRAM TRACING SIMULATION

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USE OF HIGH PERFORMANCE COMPUTING TECHNOLOGIES AND SCRIPT RUN MEDIATOR MIDDLEWARE FOR EDUCATIONAL PROCESS IN LIEPAJA UNIVERSITY 14

USE OF HIGH PERFORMANCE COMPUTING TECHNOLOGIES AND SCRIPT RU...

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14th International Scientific Conference Engineering For Rural Development

作者： Zacs, Laimonis Zigunovs, Maksims Jansone, Anita Liepaja Univ Liepaja Latvia

In this paper the authors describe a solution for implementation of the SRM (ScriptRunMediatorCSP) middleware to resolve trusting and secure connection problems to HPC (High Performance Computing) cluster resources in the Liepaja University. The main idea is to develop a specific middleware tool called SRM, which would allow connection to the parallel computing cluster system, namely to the main server masternode, to provide the easiest solution for using HPC technologies in educational processes. Cluster computing resources could be used for solution and analysis of various scientific problems applying mathematical methods and high performance technological solutions for learning and performing parallel computations in the educational process thus increasing the students' theoretical knowledge in practical applications.

关键词： cluster HPC technologies Lazarus SRM middleware parallel calculations parallel compilers

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