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Resiliency in numerical algorithm design for extreme scale simulations

INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2022年第2期36卷 251-285页

作者： Agullo, Emmanuel Altenbernd, Mirco Anzt, Hartwig Bautista-Gomez, Leonardo Benacchio, Tommaso Bonaventura, Luca Bungartz, Hans-Joachim Chatterjee, Sanjay Ciorba, Florina M. DeBardeleben, Nathan Drzisga, Daniel Eibl, Sebastian Engelmann, Christian Gansterer, Wilfried N. Giraud, Luc Goddeke, Dominik Heisig, Marco Jezequel, Fabienne Kohl, Nils Li, Xiaoye Sherry Lion, Romain Mehl, Miriam Mycek, Paul Obersteiner, Michael Quintana-Orti, Enrique S. Rizzi, Francesco Ruede, Ulrich Schulz, Martin Fung, Fred Speck, Robert Stals, Linda Teranishi, Keita Thibault, Samuel Thoennes, Dominik Wagner, Andreas Wohlmuth, Barbara INRIA Sophia Antipolis France Univ Stuttgart Stuttgart Germany KIT Karlsruher Inst Technol Karlsruhe Germany Barcelona Supercomp Ctr Barcelona Spain Politecn Milan Milan Italy Tech Univ Munich Munich Germany NVIDIA Corp Santa Clara CA USA Univ Basel Basel Switzerland Los Alamos Natl Lab Los Alamos NM USA Univ Erlangen Nurnberg Nurnberg Germany Oak Ridge Natl Lab Oak Ridge TN USA Univ Vienna Vienna Austria Univ Paris 2 Paris France Lawrence Berkeley Natl Lab Berkeley CA USA Univ Bordeaux Bordeaux France CERFACS Toulouse France Univ Politecn Valencia Valencia Spain NexGen Analyt Sheridan WY USA Australian Natl Univ Canberra ACT Australia Forschungszentrum Julich Julich Germany Sandia Natl Labs Livermore CA 94550 USA

This work is based on the seminar titled 'Resiliency in Numerical Algorithm Design for Extreme Scale Simulations' held March 1-6, 2020, at Schloss Dagstuhl, that was attended by all the authors. Advanced supercomputing is characterized by very high computation speeds at the cost of involving an enormous amount of resources and costs. A typical large-scale computation running for 48 h on a system consuming 20 MW, as predicted for exascale systems, would consume a million kWh, corresponding to about 100k Euro in energy cost for executing 10(23) floating-point operations. It is clearly unacceptable to lose the whole computation if any of the several million parallel processes fails during the execution. Moreover, if a single operation suffers from a bit-flip error, should the whole computation be declared invalid? What about the notion of reproducibility itself: should this core paradigm of science be revised and refined for results that are obtained by large-scale simulation? Naive versions of conventional resilience techniques will not scale to the exascale regime: with a main memory footprint of tens of Petabytes, synchronously writing checkpoint data all the way to background storage at frequent intervals will create intolerable overheads in runtime and energy consumption. Forecasts show that the mean time between failures could be lower than the time to recover from such a checkpoint, so that large calculations at scale might not make any progress if robust alternatives are not investigated. More advanced resilience techniques must be devised. The key may lie in exploiting both advanced system features as well as specific application knowledge. Research will face two essential questions: (1) what are the reliability requirements for a particular computation and (2) how do we best design the algorithms and software to meet these requirements? While the analysis of use cases can help understand the particular reliability requirements, the construction of remedies is

关键词： Numerical algorithms parallel computer architecture fault tolerance resilience

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The Implementation of Ray Tracing Algorithm with OpenMP parallelization

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Journal of computer and Communications 2024年第1期12卷 120-130页

作者： Noor Alnasser Raghad Alabssi Batool Faran Latifah Alessa Naya Nagy College of Computer Science and IT Imam Abdulrahman Bin Faisal University Dammam Kingdom of Saudi Arabia

Ray tracing is a computer graphics method that renders images realistically. As the name suggests, this technique primarily traces the path of light rays interacting with objects in a scene [1], permitting the calculation of lighting and reflecting impact [2]. As ray tracing is a time-consuming process, the need for parallelization to solve this problem arises. One downside of this solution is the existence of race conditions. In this work, we explore and experiment with a different, well-known solution for this race condition. Starting with the introduction and the background section, a brief overview of the topic is followed by a detailed part of how the race conditions may occur in the case of the ray tracing algorithm. Continuing with the methods and results section, we have used OpenMP to parallelize the Ray tracing algorithm with the different compiler directives critical, atomic, and first-private. Hence, it concluded that both critical and atomic are not efficient solutions to produce a good-quality picture, but first-private succeeded in producing a high-quality picture.

关键词： parallelization Ray Tracing parallel computer architecture OpenMP

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NOCA - A Notification-Oriented computer architecture: Prototype and Simulator

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IEEE ACCESS 2020年 8卷 37287-37304页

作者： Linhares, Robson R. Pordeus, Leonardo F. Simao, Jean M. Stadzisz, Paulo C. Univ Tecnol Fed Parana UTFPR Grad Program Elect Engn & Ind Informat BR-80230901 Curitiba Parana Brazil Univ Tecnol Fed Parana UTFPR Grad Program Appl Comp BR-80230901 Curitiba Parana Brazil

The Notification Oriented Paradigm (NOP) introduced a new organization of software and hardware logic based on notifications among computational entities. This NOP new organization avoids processing redundancy and allows processing unit decoupling, therefore permitting proper processing performance and processing parallelism/distribution. Thus, the NOP provides means to make efficient use of the parallel execution capabilities of modern computing systems. However, as expected, the execution dynamics of NOP, based on notifications, is not efficiently performed by the hardware of most current computing systems. This paper presents a new solution called Notification-Oriented computer architecture (NOCA), which is suitable for the execution of software developed according to the NOP computing model. The NOCA was designed according to principles of generality and scalability, which allow it to execute NOP software of any size by fetching the application from memory. The proposed architecture is organized as a fine-grained multiprocessor that hierarchically executes instructions through sets of specialized processing cores. Preliminary experiments performed on prototypal FPGA implementation of the NOCA showed the expected behavior of executing NOP applications according to its theoretical computing model. This paper also presents experiments performed on a NOCA simulator extending the scale of parallelization of applications. Results show improvements in maximizing the speedups at higher scales of parallelization, as well as minimizing the effects of processor-to-memory communication bottlenecks by reducing the number of required memory accesses during execution.

关键词： computer architecture notification-oriented paradigm parallel computer architecture computing paradigm

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FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

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IEEE ACCESS 2019年 7卷 7823-7859页

作者： Shawahna, Ahmad Sait, Sadiq M. El-Maleh, Aiman King Fahd Univ Petr & Minerals Dept Comp Engn Dhahran 31261 Saudi Arabia King Fahd Univ Petr & Minerals Res Inst Ctr Commun & IT Res Dhahran 31261 Saudi Arabia

Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolutional neural networks (CNNs) have demonstrated their effectiveness in the image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve the desired performance levels. Consequently, hardware accelerators that use application-specific integrated circuits, field-programmable gate arrays (FPGAs), and graphic processing units have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism and their energy efficiency. In this paper, we review the recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in the FPGA-based accelerators of deep learning networks. Thus, this paper is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

关键词： Adaptable architectures convolutional neural networks (CNNs) deep learning dynamic reconfiguration energy-efficient architecture field programmable gate arrays (FPGAs) hardware accelerator machine learning neural networks optimization parallel computer architecture reconfigurable computing

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Proto-cluster: A Multi-device Approach to parallel Computing 17

Proto-cluster: A Multi-device Approach to Parallel Computing

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17th IEEE World Symposium on Applied Machine Intelligence and Informatics (SAMI)

作者： Adam, Norbert Gergely, Tobias Hulic, Michal Hurtuk, Jan Mados, Branislav Tech Univ Kosice Fac Elect Engn & Informat Dept Comp & Informat Kosice Slovakia

ISBN: (纸本)9781728102504

parallel computer architectures play a significant role in the world of informatics. parallel architectures offer the one great opportunity, they offer higher computing performance than serial computers. However, higher computing performance charges higher hardware and software cost. In this publication we are looking for answers for hardware design where the price of the used assembly is low, and the performance is, on the level of robust parallel system, able to solve problems that can be calculated effectively. Our solution is presented as multi-platform architecture with different types of prototyping board connected together that create one independent parallel architecture solving one problem together.

关键词： Arduino cluster decomposition IDE parallel computer architecture Proto-cluster prototyping

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Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems

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JOURNAL OF SYSTEMS architecture 2018年 90卷 54-71页

作者： Temucin, Huseyin Imre, Kayhan M. Hacettepe Univ Dept Comp Engn Ankara Turkey

This paper presents a novel scheduling approach that efficiently schedules the computational and the communicational resources of a Software-Defined Photonic Network-on-Chip (SD-PNoC) architecture designed for high-performance real-time systems. The proposed scheduling approach extends the conventional cyclic executive scheduling algorithm from the one that schedules solely the computational resources into a general one that schedules both the computational and the communicational resources together in a synchronized manner. The proposed SD-PNoC architecture employs Software Defined Network (SDN) approach by using application specific conflict-free and contention-free communication patterns to solve the routing and wavelength assignment (RWA) problem exists in photonic networks. The implementations of the collective communication primitives such as broadcast and all-to-broadcast are also presented to demonstrate the system as a whole.

关键词： parallel computer architecture Photonic networks Routing Software defined network Optical circuit switching Real-time systems Cyclic executive scheduling

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OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator 24

OuterSPACE: An Outer Product based Sparse Matrix Multiplicat...

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24th IEEE International Symposium on High Performance computer architecture (HPCA)

作者： Pal, Subhankar Beaumont, Jonathan Park, Dong-Hyeon Amarnath, Aporva Feng, Siying Chakrabarti, Chaitali Kim, Hun-Seok Blaauw, David Mudge, Trevor Dreslinski, Ronald Univ Michigan Ann Arbor MI 48109 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781538636596

Sparse matrices are widely used in graph and data analytics, machine learning, engineering and scientific applications. This paper describes and analyzes OuterSPACE, an accelerator targeted at applications that involve large sparse matrices. OuterSPACE is a highly-scalable, energy-efficient, reconfigurable design, consisting of massively parallel Single Program, Multiple Data (SPMD)style processing units, distributed memories, high-speed crossbars and High Bandwidth Memory (HBM). We identify redundant memory accesses to non-zeros as a key bottleneck in traditional sparse matrix-matrix multiplication algorithms. To ameliorate this, we implement an outer product based matrix multiplication technique that eliminates redundant accesses by decoupling multiplication from accumulation. We demonstrate that traditional architectures, due to limitations in their memory hierarchies and ability to harness parallelism in the algorithm, are unable to take advantage of this reduction without incurring significant overheads. OuterSPACE is designed to specifically overcome these challenges. We simulate the key components of our architecture using gem5 on a diverse set of matrices from the University of Florida's SuiteSparse collection and the Stanford Network Analysis Project and show a mean speedup of 7.9x over Intel Math Kernel Library on a Xeon CPU, 13.0x against cuSPARSE and 14.0x against CUSP when run on an NVIDIA K40 GPU, while achieving an average throughput of 2.9 GFLOPS within a 24 W power budget in an area of 87 mm2.

关键词： Sparse matrix processing application-specific hardware parallel computer architecture hardware-software codesign hardware accelerators

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Dual-mode routing approach for photonic network on chip platforms

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JOURNAL OF SUPERCOMPUTING 2016年第3期72卷 904-925页

作者： Imre, Kayhan M. Hacettepe Univ Dept Comp Engn Ankara Turkey

In this paper, a dual-mode routing approach is proposed for routing messages in 2D photonic network on chip (NoC) platforms. The dual-mode routing approach is based on selecting exclusively one of two routing techniques for each stage of a parallel application. Depending on the data exchange requirements of a specific stage of an application, either a conventional per-message-based routing or a collective routing technique is selected, and the network on chip architecture is organized to support that selection. The network on chip architecture that we use is a two-dimensional torus topology built from novel non-blocking all-port photonic switches. The design of non-blocking all-port photonic switch empowers each node with simultaneous connections to four other nodes in the network. The rich connectivity provided by the switches helps the collective routing technique to efficiently support collective communication operations by allowing deadlock-free and contention-free dense data exchange among the nodes. Similar dense data exchanges are also required for some commonly known parallel algorithms such as parallel matrix multiplication, linear equation solvers and n-body simulation algorithms, just to name a few. A lightweight electronic network is employed for establishing and tearing down the photonic communication paths (light paths) in per-message-based routing technique. The lightweight electronic network is also used for coordinating the whole network in the collective routing technique.

关键词： parallel computing parallel computer architecture Photonic networks Routing Optical circuit switching

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NOCA - A Notification-Oriented computer architecture

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IEEE LATIN AMERICA TRANSACTIONS 2015年第5期13卷 1593-1604页

作者： Linhares, R. R. Simao, J. M. Stadzisz, P. C. Univ Tecnol Fed Parana UTFPR Curitiba Parana Brazil

Current software development processes lack techniques for the productive and quality design of software that makes efficient use of the parallel execution capabilities provided by the hardware of modern computing systems. In this context, the Notification Oriented Paradigm (NOP) has been recently developed aiming at a new organization of software logic based on notifications among causal-logical entities. NOP allows exploring the parallelization and/or distribution in a simpler and more efficient way than more commonly used programming paradigms. However, the execution dynamics under the NOP, based on notifications, is not efficiently performed by the hardware of current computing systems. This paper presents a new computer architecture, named NOCA, which is suitable for execution of software developed according to the NOP computing model. NOCA was designed in accordance with the principles of generality and scalability, which allow it to execute NOP software at any level of complexity by fetching it from a program memory. The developed architecture is organized as a fine grain multiprocessor that hierarchically executes instructions through sets of specialized processor cores. Preliminary experiments performed on this architecture show that NOCA presents improvements in terms of performance comparative evaluations.

关键词： Notification-Oriented Paradigm computer Architeture parallel computer architecture

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Performance and Power Analysis of High-Density Multi-GPGPU architectures: A Preliminary Case Study 17

Performance and Power Analysis of High-Density Multi-GPGPU A...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Gao, Yuxiang Iqbal, Saeed Zhang, Peng Qiu, Meikang Dell Inc Global Solut Engn Grp Round Rock TX 78682 USA SUNY Stony Brook Dept Biomed Engn Stony Brook NY 11794 USA Pace Univ Dept Comp Sci New York NY 10038 USA

ISBN: (纸本)9781479989379

A system architecture with high-density general purpose graphic processing unit (GPGPU) is emerging as a promising solution that can offer high compute performance and performance-per-watt for building cluster supercomputers. The raw compute power of these heterogeneous systems greatly exceeds the current prevailing homogenous systems, motivating their rapid adoption. These heterogeneous systems do however increase the complexity of developing parallel applications and there is a need to investigate the compute performances and associated power consumption of common benchmarks and scientific computing applications. In this paper, we present the performance and power studies through using the Dell C4130 server that integrates up to 4 GPGPU cards and NVIDIA GPGPU K80 is used. The high performance Linpack (HPL) and molecular dynamics (MD) simulators including NAMD, LAMMPS and GROMACS are tested. Through comparing 4-K80 and 2-Xeon E5-2690 v3 systems, we show that: (1) for HPL tests, the 4-GPU server delivers up to 7 TFLOPS that is 9 times faster than the 2-CPU system and its power efficiency is 4 GFLOPS per Watt;(2) for MD tests, NAMD on 4-GPU server achieves 7.8 times speedup and it uses 2.3 times power consumption compared to 2-CPU system;and LAMMPS achieves 16 times speedup and it uses 2.6 times power consumption;and GROMACS achieves 3.3 times speed up and it uses 2.6 times power consumption. These preliminary results demonstrated that the novel high-density multi-GPGPU architecture offers high performances for computing intensive applications and molecular simulators with superior power efficiencies in a space efficient design. In future, such heterogeneous architecture could be a powerful alternative solution for next generation supercomputer systems.

关键词： dense GPGPU architecture parallel computer architecture performance evaluations GPGPU power consumption

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