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14th Asian Conference on Intelligent Information and database Systems (ACIIDS)

作者： Nan Noon Noon Gettn, Janusz R. Xin, Tianbing Univ Wollongong Sch Comp & Informat Technol Wollongong NSW Australia

ISBN: (纸本)9789811982330;9789811982347

Multi-tiered persistent storage provides a logical view where all available storage is distributed over a number of levels of different speeds and capacities. Efficient scheduling of parallel data transfers in multi-tiered persistent storage is a significant problem for pipelined data processing. This work considers a class of database applications implemented as sequences of operations that transfer data between persistent storage tiers. We show how to partition the sets of data transfers to reduce the number of conflicts when data transfers are performed in parallel. The paper proposes the new rule-based algorithms for allocating parallel data transfer to the processors to minimize total processing time. The new algorithms evenly distribute the workload among the processors and reduce their idle times. We describe a number of experiments that validate the efficiency of parallel data transfer plans generated by the algorithms presented in the paper.

关键词： Multi-tiered persistent storage Scheduling parallel data processing Performance tuning database management systems

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Mode-Oriented Permutation Cipher Encryption and Passive Signal Switching Based on Multiobjective Optimized Silicon Subwavelength Metastructures

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ACS PHOTONICS 2020年第8期7卷 2163-2172页

作者： Jia, Hao Yang, Shanglin Zhou, Ting Zhang, Lei Wang, Tao Chen, Haoxiang Yang, Jianhong Yang, Lin Lanzhou Univ Sch Phys Sci & Technol Lanzhou 730000 Gansu Peoples R China Chinese Acad Sci Inst Semicond State Key Lab Integrated Optoelect Beijing 100083 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing Peoples R China

The rapid development of silicon photonics provides the possibility for various applications. In this paper, we utilize silicon subwavelength metastructures as hardware solutions for permutation cipher and signal switching. Based on the intrinsic similarities of behavior at the level of the mathematical model, we use the physical parameters of optical systems as carriers to link the feature parameters of the problems. By manipulating the evolution of optical parameters through a device, we can solve these issues in the optical field. The orthogonal mode is widely used in multimode systems. We mapped the sequence of sliced messages and signal channels to the mode orders, thus, the permutation cipher encryption, and passive signal switching problems can be refined to the arbitrary transformation of mode orders. We propose a structure fulfilling the functionality and implement the multiobjective inverse-design method to optimize the device. As a proof of concept, we adopt four modes and realize the mode transformation of TE0, TE1, TE2, and TE3 to TE2, TE0, TE3, and TE1 at a footprint cost of 4 mu m x 3.4 mu m. The simulated insertion losses are lower than 1.7 dB at 1525-1565 nm. The measured insertion losses for the fabricated device are lower than 3.1 dB. Then we demonstrate the permutation cipher encryption with a 12.5 Gbps message-rate and the passive signal switching with 40 Gbps OOK and 32G Baud PAM-4 signals. The methodology can fully release the advantages and potentials of subwavelength structures and provide a powerful tool for solving interdisciplinary problems via optics.

关键词： integrated optics silicon photonics optical metastructure parallel data processing multiplexing

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P4: Portable parallel processing Pipelines for Interactive Information Visualization

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IEEE TRANSACTIONS ON VISUALIZATION AND COMPUTER GRAPHICS 2020年第3期26卷 1548-1561页

作者： Li, Jianping Kelvin Ma, Kwan-Liu Univ Calif Davis Dept Comp Sci Davis CA 95616 USA

We present P4, an information visualization toolkit that combines declarative design specification and GPU computing for building high-performance interactive systems. Most of the existing information visualization toolkits do not harness the power of parallel processors in today's mainstream computers. P4 leverages GPU computing to accelerate both data processing and visualization rendering for interactive visualization applications. P4's programming interface offers a declarative visualization grammar for rapid specifications of data transformations, visual encodings, and interactions. By simplifying the development of GPU-accelerated visualization systems while supporting a high degree of flexibility and customization for design specification, P4 narrows the gap between expressiveness and scalability in information visualization toolkits. Through a range of examples and benchmark tests, we demonstrate that P4 provides high efficiency for creating interactive visualizations and offers drastic performance improvement over current state-of-the-art toolkits.

关键词： data visualization Graphics processing units Visualization Programming Grammar Rendering (computer graphics) data models information visualization interactive visualization parallel data processing GPU computing data exploration

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Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System

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IEEE ACCESS 2021年 9卷 59345-59352页

作者： Kang, Dongyeon Jang, Jun Tae Park, Shinyoung Ansari, Md. Hasan Raza Bae, Jong-Ho Choi, Sung-Jin Kim, Dong Myong Kim, Changwook Cho, Seongjae Kim, Dae Hwan Kookmin Univ Sch Elect Engn Seoul 02707 South Korea Kookmin Univ Circadian ICT Res Ctr Seoul 02707 South Korea Gachon Univ Dept Elect Engn Seongnam Si 13120 South Korea

Hardware-oriented neuromorphic computing is gaining great deal of interest for highly parallel data processing and superb energy efficiency, as the candidate for replacement of conventional von Neumann computing. In this work, a novel synaptic transistor constructing the neuromorphic system is proposed, fabricated, and characterized. Amorphous indium-gallium-zinc-oxide (alpha-IGZO) and Al2O3 are introduced as the channel and gate dielectric materials, respectively. Along with the high functionality and low-temperature processing viability, geometric peculiarity featuring extended gate structure improves the performances of the proposed transistor as synaptic component in the neuromorphic system. The insight into the substantial effect of optimal device structure design on energy efficiency is highlighted.

关键词： Hardware-oriented neuromorphic computing parallel data processing energy efficiency synaptic transistor amorphous indium-gallium-zinc-oxide extended gate device structure design

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Experimental Realization of a Passive Gigahertz Frequency-Division Demultiplexer for Magnonic Logic Networks

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PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS 2020年第4期14卷 1900695-1900695页

作者： Heussner, Frank Talmelli, Giacomo Geilen, Moritz Heinz, Bjoern Braecher, Thomas Meyer, Thomas Ciubotaru, Florin Adelmann, Christoph Yamamoto, Kei Serga, Alexander A. Hillebrands, Burkard Pirro, Philipp Tech Univ Kaiserslautern Fachbereich Phys & Landesforschungszentrum OPTIMA D-67663 Kaiserslautern Germany IMEC B-3001 Leuven Belgium Katholieke Univ Leuven SIEM Dept Mat Kunde B-3001 Leuven Belgium Grad Sch Mat Sci Mainz Staudingerweg 9 D-55128 Mainz Germany Japan Atom Energy Agcy Adv Sci Res Ctr Tokai Ibaraki 3191195 Japan THATec Innovat GmbH D-68165 Mannheim Germany

The emerging field of magnonics uses spin waves and their quanta, magnons, to implement wave-based computing on the micro- and nanoscale. Multifrequency magnon networks would allow for parallel data processing within single logic elements, whereas this is not the case with conventional transistor-based electronic logic. However, a lack of experimentally proven solutions to efficiently combine and separate magnons of different frequencies has impeded the intensive use of this concept. Herein, the experimental realization of a spin-wave demultiplexer enabling frequency-dependent separation of magnonic signals in the gigahertz range is demonstrated. The device is based on 2D magnon transport in the form of spin-wave beams in unpatterned magnetic films. The intrinsic frequency dependence of the beam direction is exploited to realize a passive functioning obviating an external control and additional power consumption. This approach paves the way to magnonic multiplexing circuits enabling simultaneous information transport and processing.

关键词： Brillouin light scattering frequency-division multiplexing parallel data processing spin-wave caustics wave-based logics

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Low power current-mode binary-tree asynchronous Min/Max circuit

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MICROELECTRONICS JOURNAL 2010年第1期41卷 64-73页

作者： Dlugosz, Rafal Talaska, Tomasz Swiss Fed Inst Technol Lausanne Inst Microtechnol CH-2000 Neuchatel Switzerland Univ Technol & Life Sci Fac Telecommun & Elect Engn PL-85796 Bydgoszcz Poland

A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20 mu A and data rate of 11 MHz the circuit dissipates 505 mu W, while for the signals of 200 nA and data rate of 500 kHz the power dissipation is reduced to 1 mu W. The prototype circuit with four inputs, realized in the CMOS 0.18 mu m technology, occupies the area of 1800 mu m(2). (c) 2009 Elsevier Ltd. All rights reserved,

关键词： Min/Max circuits Current-mode Asynchronous circuits parallel data processing Kohonen neural networks Nonlinear filters

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Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

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PROCEEDINGS OF THE ESTONIAN ACADEMY OF SCIENCES 2017年第3期66卷 323-335页

作者： Sklyarov, Valery Skliarova, Iouliia Rjabov, Artjom Sudnitson, Alexander Univ Aveiro Dept Elect Telecommun & Informat IEETA Campus Univ Santiago P-3810193 Aveiro Portugal Tallinn Univ Technol Sch Informat Technol Dept Comp Syst Akad Tee 15A EE-12618 Tallinn Estonia

The paper suggests and describes two architectures for parallel data sort. The first architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays - FPGA), merging preliminary sorted blocks in hardware (in the FPGA), and merging large subsets received from the FPGA in general-purpose software. data exchange between the FPGA and a general-purpose computer is organized through a fast Peripheral Component Interconnect (PCI) express bus. The second architecture is applicable to small data sets and it enables sorting to be done at the time of data acquisition, i.e. as soon as the last data item is received, the sorted items can be transferred immediately. The results of experiments clearly demonstrate the advantages of the proposed architectures that permit the reduction of the required hardware resources and increasing throughput compared to the results reported in publications and software functions targeted to data sorting.

关键词： parallel data processing merging iterative networks communication-time processing Field-Programmable Gate Array (FPGA) Peripheral Component Interconnect (PCI) express bus

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The DAQ system with a RACEway switch for the PHOBOS experiment at RHIC

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2002年第5期49卷 2455-2458页

作者： Kulinich, P Sarin, P Sukhanov, A MIT Nucl Sci Lab Cambridge MA 02139 USA Brookhaven Natl Lab Dept Chem Upton NY 11973 USA

PHOBOS data acquisition system based on a RACEway switching network is described. Occupying a single VME crate, the system utilizes 22 PPC750 CPUs working in parallel to compress data from 135 168 silicon pad detectors, and an UltraSPARC VME host for event building and data storage. Lossless Huffman coding is used for compression;this reduces the event size fourfold. The two-host disk array is used to stage data before sending them over Gigabit Ethernet to the Relativistic Heavy Ion Collider (RHIC) central computing facility. All trigger and control logic is formed using universal programmable logic VME modules, which can be programmed in situ, even when the system is running. The event building and run control software is written using the ROOT framework. The slow control and configuration makes use of an Oracle database to store configuration and monitoring parameters. The system has been taking data from the PHOBOS experiment at RHIC since June 2000. The achieved data-taking rate is 280 events/s or 28 MB/s, with additional disk arrays it can potentially reach 80 MB/s.

关键词： data acquisition (DAQ) system FPDP Huffman compression Mercury OS multihost SCSI parallel data processing power PC RACEway VME

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A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

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NEURAL NETWORKS 2012年第1期25卷 146-160页

作者： Kolasa, Marta Dlugosz, Rafal Pedrycz, Witold Szulc, Michaf Univ Technol & Life Sci Fac Telecommun & Elect Engn PL-85796 Bydgoszcz Poland Swiss Fed Inst Technol EPFL Inst Microtechnol Elect & Signal Proc Lab ESPLAB CH-2000 Neuchatel Switzerland Polish Acad Sci Space Res Ctr Mars Soc Polska PL-00716 Warsaw Poland Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada Polish Acad Sci Syst Res Inst PL-01447 Warsaw Poland Poznan Tech Univ Chair Comp Engn PL-60965 Poznan Poland

An efficient transistor level implementation of a flexible, programmable Triangular Function (TF) that can be used as a Triangular Neighborhood Function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as Application-Specific Integrated Circuit (ASIC) is presented. The proposed TNF block is a component of a larger neighborhood mechanism, whose role is to determine the distance between the winning neuron and all neighboring neurons. Detailed simulations carried out for the software model of such network show that the TNF forms a good approximation of the Gaussian Neighborhood Function (GNF), while being implemented in a much easier way in hardware. The overall mechanism is very fast. In the CMOS 0.18 mu m technology, distances to all neighboring neurons are determined in parallel, within the time not exceeding 11 ns, for an example neighborhood range, R, of 15. The TNF blocks in particular neurons require another 6 ns to calculate the output values directly used in the adaptation process. This is also performed in parallel in all neurons. As a result, after determining the winning neuron, the entire map is ready for the adaptation after the time not exceeding 17 ns, even for large numbers of neurons. This feature allows for the realization of ultra low power SOMs, which are hundred times faster than similar SOMs realized on PC. The signal resolution at the output of the TNF block has a dominant impact on the overall energy consumption as well as the silicon area. Detailed system level simulations of the SOM show that even for low resolutions of 3 to 6 bits, the learning abilities of the SUM are not affected. The circuit performance has been verified by means of transistor level Hspice simulations carried out for different transistor models and different values of supply voltage and the environment temperature - a typical procedure completed in case of commercial chips that makes the obtained results reliable. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： Neighborhood mechanism SOM parallel data processing CMOS realization Low energy consumption Asynchronous circuits

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FP-Hadoop: Efficient processing of skewed MapReduce jobs

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INFORMATION SYSTEMS 2016年第Aug./Sep.期60卷 69-84页

作者： Liroz-Gistau, Miguel Akbarinia, Reza Agrawal, Divyakant Valduriez, Patrick INRIA Montpellier Montpellier France Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

Nowadays, we are witnessing the fast production of very large amount of data, particularly by the users of online systems on the Web. However, processing this big data is very challenging since both space and computational requirements are hard to satisfy. One solution for dealing with such requirements is to take advantage of parallel frameworks, such as MapReduce or Spark, that allow to make powerful computing and storage units on top of ordinary machines. Although these key-based frameworks have been praised for their high scalability and fault tolerance, they show poor performance in the case of data skew. There are important cases where a high percentage of processing in the reduce side ends up being done by only one node. In this paper, we present FP-Hadoop, a Hadoop-based system that renders the reduce side of MapReduce more parallel by efficiently tackling the problem of reduce data skew. FP-Hadoop introduces a new phase, denoted intermediate reduce (IR), where blocks of intermediate values are processed by intermediate reduce workers in parallel. With this approach, even when all intermediate values are associated to the same key, the main part of the reducing work can be performed in parallel taking benefit of the computing power of all available workers. We implemented a prototype of FP-Hadoop, and conducted extensive experiments over synthetic and real datasets. We achieved excellent performance gains compared to native Hadoop, e.g. more than 10 times in reduce time and 5 times in total execution time. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： MapReduce data skew parallel data processing

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