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parallel decoding for burst error control codes

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 2004年第1期87卷 38-48页

作者： Fujiwara, E Namba, K Kitakami, M Tokyo Inst Technol Grad Sch Informat Sci & Engn Tokyo 1528552 Japan Univ Tokyo VLSI Design & Educ Ctr Tokyo 1138656 Japan

It is well known that sequential decoding methods for burst error control codes use Linear Feedback Shift Registers (LFSR). However, a parallel decoding method employing only combinational logic is preferable in certain applications, such as semiconductor memory systems and holographic memory systems, where a huge amount of data needs to be read or written at ultrahigh speed. This paper proposes a parallel decoding method for linear burst error control codes including the Fire code. In order to obtain the error pattern, this decoding method uses an inverse matrix of a nonsingular matrix which includes a sub-matrix of the parity check matrix. Burst error correction is possible because correct burst error patterns are obtained only from frames that completely include the burst error pattern. Furthermore, this decoding method can also be.. applied to single byte error correcting codes with less hardware. The implementation of decoding circuits for burst and byte error control codes are illustrated in this paper. And their hardware complexity is also evaluated to show that the proposed method requires less hardware than the existing parallel decoding method. Finally, we will discuss about how the proposed decoding method can be extended to correct multiple burst or byte errors. (C) 2003 Wiley Periodicals, Inc.

关键词： burst error control codes parallel decoding nonsingular matrix frames byte error control codes

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Systematic b-Adjacent Symbol Error Correcting Reed-Solomon Codes with parallel decoding 36

Systematic <i>b</i>-Adjacent Symbol Error Correcting Reed-So...

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IEEE 36th VLSI Test Symposium (VTS)

作者： Das, Abhishek Touba, Nur A. Univ Texas Austin Comp Engn Res Ctr Austin TX 78712 USA

ISBN: (纸本)9781538637746

With technology scaling, the probability of write disturbances affecting neighboring memory cells in nonvolatile memories is increasing. Multilevel cell (MLC) phase change memories (PCM) specifically suffer from such errors which affects multiple adjacent memory cells. Reed Solomon (RS) codes offer good error protection since they can correct multi-bit symbols at a time. But beyond single symbol error correction, the decoding complexity as well as the decoding latency is very high. This paper proposes a systematic b-adjacent symbol error correcting code based on Reed-Solomon codes with a low latency and low complexity parallel one step decoding scheme. A general code construction methodology is presented which can correct any errors within b-adjacent symbols. The proposed codes are compared to existing adjacent symbol error correcting Reed Solomon codes, and it is shown that the proposed codes achieve better decoder latency. The proposed codes are also shown to achieve much better redundancy compared to symbol error correcting orthogonal Latin square (OLS) codes.

关键词： adjacent symbol error correction Reed Solomon codes parallel decoding phase change memories multilevel cell

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Asynchronously parallel decoding For Automatic Speech Recognition Services 18

Asynchronously Parallel Decoding For Automatic Speech Recogn...

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18th International Joint Conference on Computer Science and Software Engineering (JCSSE) - Cybernetics for Human Beings

作者： Kurpukdee, Nattapong Boonkla, Surasak Sertsi, Phuttapong Chunwijitra, Vataya Natl Sci & Technol Dev Agcy NSTDA NECTEC 112 Thailand Sci Pk Amphoe Khlong Luang 12120 Pathum Thani Thailand

ISBN: (纸本)9781665438315

We proposed a new automatic speech recognition (ASR) service architecture that is extendable to medium-scale ASR service and more flexible than the previous architecture. Improvement aims to substitute the distributed processing approach with an asynchronous parallel thread for decoding multiple voice streams. We replace our TCP-based communication protocol with a remote procedure call developed by Google (gRPC) that makes our ASR service become a developer-friendly, less overhead connection. Besides, the API gateway is employed to reinforce the ASR services by multiple servers so that we can increase our new ASR service to a larger scale. The experimental result shows that our new architecture performs faster than the previous architecture in terms of real-time factor.

关键词： parallel decoding Automatic speech recognition

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Fast and parallel decoding for Transducer 48

Fast and Parallel Decoding for Transducer

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48th IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2023

作者： Kang, Wei Guo, Liyong Kuang, Fangjun Lin, Long Luo, Mingshuang Yao, Zengwei Yang, Xiaoyu Zelasko, Piotr Povey, Daniel Xiaomi Corp. Beijing China Meaning.Team Inc United States

ISBN: (纸本)9781728163277

The transducer architecture is becoming increasingly popular in the field of speech recognition, because it is naturally streaming as well as high in accuracy. One of the drawbacks of transducer is that it is difficult to decode in a fast and parallel way due to an unconstrained number of symbols that can be emitted per time *** this work, we introduce a constrained version of transducer loss to learn strictly monotonic alignments between the sequences;we also improve the standard greedy search and beam search algorithms by limiting the number of symbols that can be emitted per time step in transducer decoding, making it more efficient to decode in parallel with batches. Furthermore, we propose an finite state automaton-based (FSA) parallel beam search algorithm that can run with graphs on GPU efficiently. The experiment results show that we achieve slight word error rate (WER) improvement as well as significant speedup in decoding. Our work is open-sourced and publicly available1 © 2023 IEEE.

关键词： beam search end-to-end parallel decoding speech recognition transducer

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RESEARCH OF parallel decoding ALGRITHM IN H.264 ON TILE64

RESEARCH OF PARALLEL DECODING ALGRITHM IN H.264 ON TILE64

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2nd IEEE International Conference on Broadband Network and Multimedia Technology

作者： Guan Hui Wang Hongpeng Harbin Inst Technol Shenzhen Grad Sch Shenzhen Peoples R China

ISBN: (纸本)9781424450053

Due to the increasing performance requirements of decoding H.264/AVC in High Definition (HD) or larger resolution videos, new approaches are necessary to realize real-time processing. With the development of multi-core architecture, it's efficient to adopt parallel decoding in the multicore processor environment. According to the characteristics of H.264/AVC standard, this paper analyses the parallelism of decoding algorithm, designs a parallelization approach of Hybrid decomposition, and implements parallel decoding based on the TILE64 multi-core processor. The experiment result proves that the performance of decoder can be improved greatly.

关键词： H.264 real-time multi-core processor parallel decoding TILE64

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A tree-based model with branch parallel decoding for handwritten mathematical expression recognition

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PATTERN RECOGNITION 2024年 149卷

作者： Li, Zhe Yang, Wentao Qi, Hengnian Jin, Lianwen Huang, Yichao Ding, Kai South China Univ Technol 381 wushan Rd Guangzhou Peoples R China Huzhou Univ 759Erhuandong Rd Huzhou 313000 Peoples R China IntSig Informat Co 1268Wanrong Rd Shanghai 200040 Peoples R China South China Univ Technol Sch Elect & Informat Guangzhou Peoples R China

Handwritten mathematical expression recognition (HMER) is a challenging task in the field of computer vision due to the complex two-dimensional spatial structure and diverse handwriting styles of mathematical expressions (MEs). Recent mainstream approach treats MEs as objects with tree structures, modeled by sequence decoders or tree decoders. These decoders recognize the symbols and relationships between symbols in MEs in depth-first order, resulting in long decoding steps that can harm their performance, particularly for MEs with complex structures. In this paper, we propose a novel tree-based model with branch parallel decoding for HMER, which parses the structures of ME trees by explicitly predicting the relationships between symbols. In addition, a query constructing module is proposed to assist the decoder in decoding the branches of ME trees in parallel, thus reducing the number of decoding time steps and alleviating the problem of long sequence attention decoding. As a result, our model outperforms existing models on three widely-used benchmarks and demonstrates significant improvements in HMER performance.

关键词： Handwritten mathematical expression recognition Tree-based model parallel decoding Attention mechanism

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Review of parallel decoding of Space-time Block Codes toward 4G Wireless and Mobile Communications

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Procedia Computer Science 2013年 19卷 1059-1067页

作者： Elie Amani Karim Djouani Anish Kurien FSATI/Department of Electrical Engineering Tshwane University of Technology (TUT) Pretoria 0001 South Africa Université Paris-Est Créteil (UPEC) 12/LISSI Lab Créteil France

This paper presents a review of recent developments in the area of STBC decoding particularly parallel decoding of full-rate full-diversity STBCs toward real-time 4G wireless communications. After reviewing some parallel STBC decoding techniques and presenting one of the most promising types of parallel processors suitable for the 4G SDR the SIMD processor, the paper shows that parallel decoding of the Golden Code on the ClearSpeed CSX700 SIMD processor achieves a speedup of up to 30 times. The paper highlights the potential to achieve real-time decoding of high-rate STBCs with the use of robust parallel processors.

关键词： Data level parallelism (DLP) Multiple-input multiple-output (MIMO) parallel decoding single-instruction multiple- data (SIMD) processor Software Defined Radio (SDR) Space-Time Block Code (STBC).

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A New Shift-Add Secret Sharing Scheme for Partial Data Protection With parallel Zigzag decoding

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2024年 19卷 10221-10232页

作者： Chen, Jiajun Shen, Yichen Sung, Chi Wan City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China

This paper studies distributed storage for protecting the confidentiality of partial data in the presence of storage node failures. It is required that not only the original data can be reconstructed from the remaining surviving nodes, but also the data lost by a failed node can be repaired from as few nodes as possible. The minimum number of surviving nodes required to repair a failed node is called the repair degree. Inspired by the zigzag-decodable secret sharing scheme, we propose a new shift-add secret sharing scheme based on the XOR and bitwise-shift operations, in which confidential data is protected by using random keys generated from non-confidential data. The reliability and repairability of the proposed scheme are measured by the message loss probability and the maximum repair degree among all nodes, respectively, and then compared with three benchmark schemes. In contrast to conventional zigzag-decodable codes, the special structure of our proposed scheme allows the design of fast parallel algorithms for modern devices with multi-core processors, which have a linear speedup in decoding time compared with various versions of serial zigzag decoding. Experiments are implemented on a multi-core computer, and the empirical results on decoding time are consistent with our theoretical observations.

关键词： Codes decoding Maintenance engineering Cryptography Reliability Redundancy Encoding Polynomials Multicore processing Loss measurement Secret sharing zigzag decoding parallel decoding node repair

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RESEARCH OF parallel decoding ALGRITHM IN H.264 ON TILE64

RESEARCH OF PARALLEL DECODING ALGRITHM IN H.264 ON TILE64

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2009 2nd IEEE International Conference on Broadband Network & Multimedia Technology（IC-BNMT2009）

作者： Guan Hui,Wang Hongpeng Harbin Instute of Technology Shenzhen Graduate School,Shenzhen

Due to the increasing performance requirements of decoding H.264/AVC in High Definition (HD) or larger resolution videos,new approaches are necessary to realize real-time *** the development of multi-core architecture,it's efficient to adopt parallel decoding in the multicore processor *** to the characteristics of H.264/AVC standard,this paper analyses the parallelism of decoding algorithm,designs a parallelization approach of Hybrid decomposition,and implements parallel decoding based on the TILE64 multi-core *** experiment result proves that the performance of decoder can be improved greatly.

关键词： H.264 real-time multi-core processor parallel decoding TILE64

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Balanced codes with parallel encoding and decoding

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IEEE TRANSACTIONS ON COMPUTERS 1999年第8期48卷 794-814页

作者： Tallini, LG Bose, B Politecn Milan Dipartimento Tec I-20133 Milan Italy Oregon State Univ Dept Comp Sci Corvallis OR 97331 USA

A balanced code with k information bits and r check bits is a binary code of length n = k + r and cardinality 2(k) such that the number of Is in each code word is equal to right perpendicular n/2 left perpendicular. This paper describes the design of efficient balanced codes with parallel encoding and parallel decoding. In this case, since area and delay of such circuits are critical factors, another parameter is introduced in the definition of balanced code: the "number of balancing functions used in the code design," p. parallel encoding and decoding algorithms independent from the chosen balancing method are given and these can be implemented by a VLSI circuit of size O(pk) and depth O(logp). This paper also presents a new balancing method: the permutation method, which, for infinitely many values of k (such as, k = 8, 10, 20, 22, 32, 34,...) is more efficient than Knuth's complementation method. This new method results in efficient balanced codes with k information bits, k even, r = 2 right perpendicular k/12 left perpendicular + 2 check bits and p = 6 balancing functions. Further, Knuth's complementation method is generalized to obtain efficient code designs for any value of the parameters k, r, and p, provided that [GRAPHICS] where m is such that [GRAPHICS]

关键词： balanced codes constant weight codes parallel encoding parallel decoding VLSI systems

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