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IEEE International Conference on Industrial Technology (ICIT)

作者： Amani, Elie Djouani, Karim Kurien, Anish Tshwane Univ Technol FSATI Dept Elect Engn ZA-0001 Pretoria South Africa

ISBN: (纸本)9781467345675;9781467345682

The Golden Code is an optimum full-rate full-diversity STBC for 2x2 MIMO communication systems. But its optimal decoding suffers high complexity. Due to the benefits it may provide if practically implemented, reducing its decoding complexity has been of interest in recent research. One of the decoders with reduced complexity that have been proposed lately has essentially ML performance and achieves a worst-case complexity of O(N-2), where N is the underlying QAM constellation size. In this paper, a parallel implementation approach for this fast essentially ML decoder is proposed. This approach is mapped on low-power processors of the SIMD type, such as the ClearSpeed CSX700. The CSX700 decoding runs up to 30 times faster than sequential decoding on a CPU. This result reveals the potential to achieve real-time low-power ML decoding of the Golden Code with the use of the suitable number of processors.

关键词： Golden Code maximum likelihood (ML) decoding parallel decoding single instruction multiple data (SIMD) Space-Time Block Code (STBC)

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parallel Algorithmic Optimization for Enhanced Quasi-Maximum Likelihood decoding on GPU

Parallel Algorithmic Optimization for Enhanced Quasi-Maximum...

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2nd IEEE International Conference on Electronics and Communication Engineering (ICECE)

作者： Kong Fei-yue Wan Xue-fen Chen Si-jing Yang Yi DongHua Univ Shanghai Peoples R China North China Inst Sci & Technol Langfang Hubei Peoples R China Wuhan Maritime Commun Res Inst Wuhan Peoples R China

ISBN: (数字)9781728147840

ISBN: (纸本)9781728147840

The Enhanced quasi-maximum likelihood (EQML) decoder has better decoding performance than the traditional belief propagation (BP) decoder, but its decoding speed is greatly reduced due to its complicated computational structure. Therefore, an efficient graphics processing unit (GPU) implementation structure for EQML decoder of low-density parity-check (LDPC) code is proposed. Intra-codeword parallel and inter-codeword parallel decoding schemes on GPU are adopted instead of serial decoding on CPU. Several optimization methods have also been employed to enhance the decoder throughput, such as compressed storing and Kernel thread arrangement scheme, which improve the decoding speed without degrading the decoding performance of the decoder. Experiment results show that our GPU based implementation structure which is about two orders of magnitude faster than that of CPU implementation.

关键词： LDPC code GPU EQML decoder parallel decoding BP decoder

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parallel Maximum Likelihood decoding of the Golden Code on Low-Power SIMD Coprocessor

Parallel Maximum Likelihood Decoding of the Golden Code on L...

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IEEE International Conference on Industrial Technology

作者： Elie Amani Karim Djouani Anish Kurien F'SATI/ Dept. of Electrical Engineering Tshwane University of Technology (TUT) Pretoria 0001 South Africa

ISBN: (纸本)9781467345675

The Golden Code is an optimum full-rate full-diversity STBC for 2×2 MIMO communication systems. But its optimal decoding suffers high complexity. Due to the benefits it may provide if practically implemented, reducing its decoding complexity has been of interest in recent research. One of the decoders with reduced complexity that have been proposed lately has essentially ML performance and achieves a worst-case complexity of O(N~2), where N is the underlying QAM constellation size. In this paper, a parallel implementation approach for this fast essentially ML decoder is proposed. This approach is mapped on low-power processors of the SIMD type, such as the ClearSpeed CSX700. The CSX700 decoding runs up to 30 times faster than sequential decoding on a CPU. This result reveals the potential to achieve real-time low-power ML decoding of the Golden Code with the use of the suitable number of processors.

关键词： Golden Code maximum likelihood (ML) decoding parallel decoding single instruction multiple data (SIMD) Space-Time Block Code (STBC) maximum likelihood decoding LOW POWER single instruction multiple datastream decoding decoders Coprocessors Computer Programming Languages Codes PROCESSOR sequential decoding

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On a space time parallel iterative coding scheme and its performance evaluation

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WIRELESS COMMUNICATIONS & MOBILE COMPUTING 2003年第5期3卷 629-639页

作者： Hou, J Lee, MH Chonbuk Natl Univ Sch Elect Informat Engn Inst Informat & Commun Chonju 561756 South Korea

This paper proposes a class of space time parallel (STP) iterative coding scheme to combat fading for wireless MIMO systems. In addition to the inner iterations, the super iterations (or outer iterations) and symbol interleaved space time coding are employed to achieve additional time diversity and coding gain in fading channel. The numerical and simulation results demonstrate that the STP iterative coding scheme may make use of all the advantages of transmit diversity and time diversity in wireless MIMO systems. In particular, in the case of STP turbo codes, about I dB BER enhancement and half calculation time reduction from conventional space time (ST) turbo codes designs are achieved;in the case of low density parity check (LDPC) codes, about 0.8 dB improvement from conventional ST LDPC designs is obtained. Copyright (C) 2003 John Wiley Sons, Ltd.

关键词： space time coding iterative coding parallel decoding

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Area-efficient high-speed decoding schemes for turbo decoders

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2002年第6期10卷 902-912页

作者： Wang, ZF Chi, ZP Parhi, KK Natl Semicond Corp Longmont CO 80501 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN USA

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

关键词： area efficient high speed Maximum a posteriori (MAP) algorithm parallel decoding turbo code very large scale integration (VLSI)

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Hard Successive Interference Cancellation for M-QAM MIMO Links in the Presence of Rayleigh Deep-Fading

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SENSORS 2024年第15期24卷 5038页

作者： Elgam, Avner Klemfner, Meir Silon, Shachar Peretz, Yossi Pinhasi, Yosef Ariel Univ Fac Engn IL-40700 Ariel Israel Lev Acad Ctr Jerusalem Coll Technol Dept Comp Sci IL-9372115 Jerusalem Israel

In our paper, we propose a generalized version of the Alternating Projections Digital Hard Successive Interference Cancellation (AP-HSIC) algorithm that is capable of decoding any order of constellation M in an M-Quadrature Amplitude Modulation (QAM) system. Our approach applies to Rayleigh deep-fading Multiple-Input Multiple-Output (MIMO) channels with high-level Additive White Gaussian Noise (AWGN). It can handle various destructive phenomena without restricting the number of antenna arrays in the transmitter/receiver. Importantly, it does not rely on closed-loop MIMO feedback or the need for Channel-State Information Transmission (CSIT). We have demonstrated the effectiveness of our approach and provided a Bit Error Rate (BER) analysis for 16-, 32-, and 64-QAM modulation systems. Real-time simulations showcase the differences and advantages of our proposed algorithm compared to the Multi-Group Space-Time Coding (MGSTC) decoding algorithm and the Lagrange Multipliers Hard Successive Interference Cancellation (LM-HSIC) algorithm, which we have also developed here. Additionally, our paper includes a mathematical analysis of the LM-HSIC algorithm. The AP-HSIC algorithm is not only effective and fast in decoding, including interference cancellation computational feedback, but it can also be integrated with any Linear Processing Complex Orthogonal Design (LPCOD) technique, including Complex Orthogonal Design (COD) schemes such as high-order Orthogonal Space-Time Block Code (OSTBC) with high-order QAM symbols.

关键词： M-QAM MIMO Rayleigh deep-fading interference cancellation parallel decoding computational feedback

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parallel Implementation of the CCSDS Turbo Decoder on GPU

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China Communications 2024年第10期21卷 70-77页

作者： Liu Zhanxian Liu Rongke Zhang Haijun Wang Ning Sun Lei Wang Jianquan School of Computer&Communication Engineering University of Science and Technology BeijingBeijing 100083China School of Electronic and Information Engineering Beihang UniversityBeijing 100191China Beijing Engineering and Technology Research Center for Convergence Networks and Ubiquitous Services Institute of Artificial IntelligenceUniversity of Science and Technology BeijingBeijing 100083China School of Information Engineering Zhengzhou UniversityZhengzhou 450001China School of Automation and Electrical Engineering University of Science and Technology BeijingBeijing 100083China

This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)***,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism *** mitigate this issue,we propose a padding method that inserts several bits before the information frame *** obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are *** presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small *** proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.

关键词： CCSDS CUDA GPU parallel decoding turbo codes

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A Single and Adjacent Error Correction Code for Fast decoding of Critical Bits

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IEEE TRANSACTIONS ON COMPUTERS 2018年第10期67卷 1525-1531页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba 2638522 Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

Many systems have critical bits which must be decoded at high speeds;for example, flags to mark the start and end of a packet (SOP and EOP) determine subsequent actions, thus they must be decoded first and fast. This paper presents a new single and adjacent error correction (SAEC) code;as the codewords have critical bits, the proposed code accomplishes a fast decoding for them. The proposed code is a systematic code and permits shortening. This is accomplished by reducing the information bits, so that columns in the H matrix can be eliminated, while still keeping both the SAEC capability and the systematic feature, but for an odd number of information bits, an adjustment step in critical bits is required. It is shown that the check bit length of the proposed code is nearly the same as that of the traditional (optimal) Hamming SAEC code. The decoder of the proposed SAEC code is compared with the traditional Hamming SAEC code;this comparison shows that on average, the delay time for the critical bits is reduced by 6 percent compared with the traditional Hamming SAEC code (so at the same reduction level as a previous SEC scheme for fast decoding of critical bits over a traditional SEC code). Also, the area and power consumption of the proposed decoder show average reductions of 12 percent and 10 percent compared with the decoder of a traditional SAEC code.

关键词： Error correction code (ECC) adjacent error correction parallel decoding critical bits

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parallelized deblocking filtering of HEVC decoders based on complexity estimation

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2016年第2期12卷 369-382页

作者： Jo, Hyunho Park, Seanae Sim, Donggyu Kwangwoon Univ Dept Comp Engn 20 Gwangun Ro Seoul South Korea

This paper proposes a parallelization method for a deblocking filter in a high-efficiency video coding (HEVC) decoder based on complexity estimation. A deblocking filter of HEVC is generally considered to be appropriate for data-level parallelism (DLP) because there are no data-level dependencies among adjacent blocks in the horizontal and vertical filtering processes. However, an imbalanced workload can increase the idle time on some of the threads, and thus, the maximum parallel performance cannot be achieved with only DLP. To alleviate this problem, the proposed method estimates the computational complexity by utilizing the coding unit (CU) segment information and the on/off flag of the deblocking filter in advance. Then, the workload is distributed equally across all threads. The experimental results indicate that the proposed method can accelerate the decoding speed by a factor of 3.97, with six threads on top of the sequential deblocking filtering. In addition, the ratio of the maximum elapsed time to ideal elapsed time is reduced to approximately 21 %, as compared to conventional DLP-based parallel deblocking filtering methods that do not implement a complexity estimation method.

关键词： HEVC Deblocking filter parallel decoding Workload imbalance

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decoding ALGORITHMS WITH INPUT QUANTIZATION AND MAXIMUM ERROR-CORRECTION CAPABILITY

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IEEE TRANSACTIONS ON INFORMATION THEORY 1995年第4期41卷 1126-1133页

作者： HASSAN, A STARK, W UNIV MICHIGAN DEPT ELECT & COMP SYST ENGNANN ARBORMI 48109

In this correspondence, decoding that uses soft-decision information but with multiple low-complexity decoders are investigated. These decoders correct only errors and erasures. The structure of the receiver consists of a bank of z demodulators followed by errors- and erasures-correcting decoders operating in parallel. Each demodulator has a threshold for determining when to erase a given symbol. We assign a cost f(theta) to the noise for causing an erasure when the receiver uses a particular threshold theta and a (larger) cost f(theta) for causing an error. The goal in designing the receiver is to choose the thresholds to maximize the noise cost which is necessary to cause a decoding error. We demonstrate that the above formulation is solvable for many channels including the M-ary input-output channel, the additive channel with coherent demodulation, and an additive channel with orthogonal modulation and noncoherent demodulation. Then we show that the maximum worst case error-correcting capability of the parallel decoding algorithms is the same as the maximum worst case error-correcting capability of a correlation decoder with the same number of quantization regions.

关键词： SOFT-DECISION decoding parallel decoding CONCATENATED CODES QUANTIZATION CORRELATION decoding COMMUNICATIONS GAIN

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