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3.8-Gbps Polar Belief Propagation Decoder on GPU

IEEE COMMUNICATIONS LETTERS 2023年第5期27卷 1247-1251页

作者： Chen, Yuxing Qiao, Xinyuan Deng, Keyue Song, Suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China

In this work, a high-throughput belief propagation (BP) decoder of polar codes on graphics processing unit (GPU) is proposed for software-defined communication systems. The decoder is jointly optimized from algorithm and architecture aspects. From the algorithm aspect, the storage pattern and computation flow are optimized to reduce complexity. From the architecture aspect, different granularities of parallelism are extensively exploited to achieve high throughput. Equipped with these techniques, a high-speed GPU-based BP decoder is developed, and experimental results show that the proposed decoder can improve the normalized throughput by 64.1% to 294.1% compared to the state-of-the-art GPU-based BP decoder.

关键词： decoding Polar codes Graphics processing units Iterative decoding Complexity theory Throughput parallel processing Polar code GPU low-complexity design parallel decoding belief propagation

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Hidden Markov Modeling for Semantic Analysis-On the Combination of Different decoding Strategies

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INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2005年第3期8卷 295-305页

作者： Beuschel, Christiane Minker, Wolfgang Buehler, Dirk Univ Ulm Dept Informat Technol Ulm Germany

Different strategies to enhance the semantic decoding accuracy of a stochastic parser are discussed and comparatively evaluated on a corpus containing dialogues between two persons scheduling a meeting. Using a stochastic parsing method the human effort can be limited to the task of data labeling, which is much simpler than the design, maintenance and extension of grammar rules, especially for non-experts. Since a stochastic method automatically learns the semantic formalism through an analysis of these data, it is comparatively flexible and robust and can easily be ported to different applications, domains and human languages. The performance of the parser was improved by subsequently adding valuable and removing redundant semantic information, as well as by combining several decoding methods either sequentially or in parallel.

关键词： semantic representation confidence model topology context parallel decoding sequential decoding stochastic parsing spoken language Hidden Markov Model Viterbi algorithm

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Design of balanced and constant weight codes for VLSI systems

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IEEE TRANSACTIONS ON COMPUTERS 1998年第5期47卷 556-572页

作者： Tallini, LG Bose, B Univ Salerno Dipartimento Informat & Applicaz I-84081 Baronissi Salerno Italy Oregon State Univ Dept Comp Sci Corvallis OR 97331 USA

A constant weight, w, code with k information bits and r check bits is a binary code of length n = k + rand cardinality 2(k) such that the number of Is in each code word is equal to w. When w = [n/2], the code is called balanced. This paper describes the design of balanced and constant weight codes with parallel encoding and parallel decoding. Infinite families of efficient constant weight codes are given with the parameters k, r, and the "number of balancing functions used in the code design," p. The larger p grows, the smaller r will be;and the codes can be encoded and decoded with VLSI circuits whose sizes and depths are proportional to pk and log:! p, respectively. For example, a design is given for a constant weight w = 33 code with k = 64 information bits, r = 10 check bits, and p = 8 balancing functions. This code can be implemented by a VLSI circuit using less than 4,054 transistors with a depth of less than 30 transistors.

关键词： constant weight codes balanced codes parallel encoding parallel decoding VLSI systems

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Successive-Cancellation List Decoder of Polar Codes Based on GPU 3

Successive-Cancellation List Decoder of Polar Codes Based on...

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3rd IEEE International Conference on Computer and Communications (ICCC)

作者： Han, Xu Liu, Rongke Liu, Zhanxian Zhao, Ling Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China CETC Key Lab Aerosp Informat Applicat Shijiazhuang Hebei Peoples R China

ISBN: (纸本)9781509063529

In this paper, a Graphics Processing Unit (GPU) implementation of a Successive-Cancellation List (SCL) decoder for polar codes is proposed. Based on the compute unified device architecture (CUDA), the strategy to parallelize the decoding procedure is designed to reduce the latency. Moreover, the optimal design of data structures for several kinds of intermediate information is presented. In order to reduce the global memory accesses in list pruning, The GPU-adapted lazy-copy strategy is elaborated. By means of the parallel computing capabilities of GPUs, the proposed decoder achieves high throughput of 41Mbps on NVIDIA GTX 980 and 65Mbps on TITAN X while decoding the code with length of 1024 bits and 32 lists.

关键词： GPU CUDA polar codes SCL parallel decoding

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Improved Decoder by Partially Permuted Factor Graphs of Polar Codes 14

Improved Decoder by Partially Permuted Factor Graphs of Pola...

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14th IEEE International Conference on Wireless Communications and Signal Processing (WCSP)

作者： Cui, Hongji Niu, Kai Ren, Junwei Beijing Univ Posts & Telecommun Key Lab Univ Wireless Commun Minist Educ Beijing Peoples R China Peng Cheng Lab Dept Broadband Commun Shenzhen Peoples R China Samsung Res China Beijing SRC B Beijing 100028 Peoples R China

ISBN: (纸本)9781665450850

We study the structure of the factor graph of polar codes, and propose some improved decoding algorithms for polar codes based on the equivalence of partially permuted factor graphs (PPFG). Different from the previously proposed permuted factor graphs, PPFG proposed in this paper divides the polar code into shorter codewords, each sub-code is permuted into a different factor graph, and finally combined into an equivalent PPFG. We first prove the equivalence of PPFG. Then an algorithm for searching optimal factor graphs is proposed. Finally, we propose a series of algorithms based on PPFG such as optimal PPFG SC/BP, SC parallel list (SCPL) and parallelly permuted SC list (PPSCL). Simulation results show that under the same complexity and delay, the performance of the optimal PPFG SC has a 0.25dB gain compared with the original SC decoding algorithm at the code length N = 64. Algorithms such as SCPL have similar performance to SCL, but SCPL does not require sorting and path expansion.

关键词： polar codes permuted factor graphs successive cancellation parallel decoding

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GPU-BASED IMPLEMENTATION OF BELIEF PROPAGATION decoding FOR POLAR CODES 44

GPU-BASED IMPLEMENTATION OF BELIEF PROPAGATION DECODING FOR ...

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44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Liu, Zhanxian Liu, Rongke Yan, Zhiyuan Zhao, Ling Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA

ISBN: (纸本)9781479981311

Belief Propagation (BP) decoding provides soft outputs and features high-level parallelism. In this paper, we propose an optimized software BP decoder for polar codes on graphics processing units (GPUs). A full-parallel decoding architecture for codes with length n <= 2048 is presented to simultaneously update n/2 processing elements (PEs) within each stage and achieve high on-chip memory utilization by using 8-bit quantization. And, for codes with length n > 2048, a partial-parallel decoding architecture is proposed to partly update PEs of each stage in parallel and coalesced global memory accesses are performed. Experimental results show that, with incorporation of the G-matrix based early termination criterion, more than 1 Gbps throughput for codes n <= 1024 can be achieved on NVIDIA TITAN Xp at 5 dB while the decoding latency is less than 1 ms. Compared with the state-of-the-art works, the proposed decoder achieves throughput speedups from 2.59x to 131x and provides good tradeoff between error performance and throughput.

关键词： Polar code CUDA SIMT parallel decoding GPU

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Hybrid parallelization for HEVC Decoder

Hybrid Parallelization for HEVC Decoder

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6th International Congress on Image and Signal Processing (CISP)

作者： Jo, Hyunho Sim, Donggyu Jeon, Byeungwoo Kwangwoon Univ Seoul South Korea Sungkyunkwan Univ Sch Elect & Elect Engn Suwon South Korea

ISBN: (纸本)9781479927630

This paper presents a new hybrid parallelization method for High Efficiency Video Coding (HEVC) decoder. The proposed method groups HEVC decoding modules into entropy decoding, pixel decoding, and in-loop filtering parts for optimal parallelization considering the characteristic of all the parts. The proposed method employs coding tree unit (CTU)-level 2D wavefront for the pixel decoding part. To decrease the delay between the entropy decoding and pixel decoding, task level parallelism (TLP) is additionally employed for two parts. For the HEVC deblocking filter, CTU-level data level parallelism (DLP) with equally partitioned CTUs is proposed. In addition, CTU row-level DLP for sample adaptive offset (SAO) is proposed to achieve maximum parallel performance and to minimize the overhead of organizing a backup buffer. The experimental results show that the proposed approach for parallel deblocking filter achieved a speed-up of 5.4x and the parallel SAO approach achieved a speed-up of 3.7x maximally on the multi-core platform. Furthermore, the proposed parallel HEVC decoder shows a speed-up of 2.9x with 6 threads without any encoder parallel tools such as wavefront parallel processing (WPP) coding and picture partitioning with tile and slice segments.

关键词： component HEVC Video coding parallel decoding

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Improvements for decoding Algorithm of Turbo Product Code

Improvements for Decoding Algorithm of Turbo Product Code

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IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

作者： Li, Lintao Zhang, Fei Zheng, Peng Yang, Zhiliang Beijing Inst Technol Sch Informat & Elect Beijing Peoples R China

ISBN: (纸本)9781479952748

On the basis of Lu's syndrome-based decoding algorithm, we propose an improved decoding algorithm for turbo product code, which has lower complexity and latency. On one hand, the proposed algorithm further reduces the computational complexity and the decoding latency by simplifying the calculation of syndrome and selecting a proper number of least reliable bits. On the other hand, this algorithm obtains extra coding gain by using a stricter judgment condition. Finally, we apply our algorithm to the parallel decoding structure. Simulation results demonstrate that the proposed algorithm can reduce the complexity and latency effectively at the cost of less than 0.1dB BER performance degradation, so it is very suitable for these delay-sensitive applications.

关键词： TPC syndrome-based algorithm parallel decoding low latency

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TILES FOR MANAGING COMPUTATIONAL COMPLEXITY OF VIDEO ENCODING AND decoding

TILES FOR MANAGING COMPUTATIONAL COMPLEXITY OF VIDEO ENCODIN...

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29th Picture Coding Symposium (PCS)

作者： Fuldseth, Arild Horowitz, Michael Xu, Shilin Misra, Kiran Segall, Andrew Zhou, Minhua Cisco Systems United States EBrisk Video United States Sharp Laboratories of America United States Texas Instruments United States

ISBN: (纸本)9781457720482

In this paper, we introduce the concept of tiles. Tiles are incorporated into the current design of the High Efficiency Video Coding (HEVC) standard being developed by the Joint Collaborative Team on Video Coding (JCT-VC). In the design, tiles are introduced to support high-level parallelism and also to reduce on-chip memory requirements. This paper describes the tile concept and reports results due to the technique.

关键词： Intra prediction Video coding parallel decoding

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New Iterative decoding Algorithms of 2D Product Block Codes

New Iterative Decoding Algorithms of 2D Product Block Codes

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World Congress on Computer Applications and Information Systems (WCCAIS)

作者： Ahmadi, Abdeslam El Bouanani, Faissal Ben-Azza, Hussain ENSAM Dept Ind & Prod Engn Meknes Morocco ENSIAS Dept Commun Networks Rabat Morocco

ISBN: (纸本)9781479933518

This paper presents four new iterative decoders for two dimensional product block codes (2D-PBC) based on Genetic Algorithms. Each of these iterative decoders runs in parallel on a number of processors connected by a network. They have almost the same complexity as the conventional iterative decoder, but their performances are improved since at each iteration, they trap the better of extrinsic information computed by the elementary decoders running simultaneously on all processors.

关键词： Error Correcting Codes Product Block Codes Genetic Algorithms parallel decoding Ierative decoding Time Complexity

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