Guessing random additive noise decoding (GRAND) is a noise-centric universal algorithm that is suitable for linear block codes. Using the guessing decoding independence of GRAND-Markov order (GRAND-MO), in this paper,...
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Guessing random additive noise decoding (GRAND) is a noise-centric universal algorithm that is suitable for linear block codes. Using the guessing decoding independence of GRAND-Markov order (GRAND-MO), in this paper, a serial-storing and parallel-crossing configured high throughput GRAND-MO decoding scheme is proposed. Subsequently, the key permutation generation module, the noise error patterns (NEPs) generation module and the guessing decoding module, are each elucidated through a comprehensive step-by-step approach. The NEPs generation module outputs patterns solely based on burst parameters. For the targeted cyclic redundancy check (CRC) codes, the error detection capability is jointly integrated with GRAND-MO for error correction. Compared to conventional linear block codes, simulation results show the error correction capability of CRC is significantly improved. Given a packet length of 128 bits and a clock frequency of 866 MHz, field programmable gate array (FPGA) implementation shows that the NEPs generation throughput can reach 14.6 Gbps under the 128 parallelism assumption. The throughput can be flexibly adjusted to satisfy different throughput requirements at the cost of increased hardware overhead. This work serves as a practical reference for future research in GRAND-MO.
Iterative process is a general principle in decoding powerful FEC codes such as turbo codes. However, the mutual information exchange during the iterative process is not easy to analyze and to describe. A useful techn...
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Iterative process is a general principle in decoding powerful FEC codes such as turbo codes. However, the mutual information exchange during the iterative process is not easy to analyze and to describe. A useful technique to help the designer is the EXtrinsic Information Transfer (EXIT) chart. Unfortunately, this method cannot be directly applied to the decoding convergence analysis if parallel processing has to be exploited for the design of turbo decoders. In this letter, an extension of the EXIT charts method is proposed in order to take into account the constraints introduced by parallel implementations. The corresponding analysis associated with Monte-Carlo simulations gives additional understanding of the convergence process for the design of parallelarchitectures dedicated to turbo decoding.
In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a paralleldecoding struct...
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In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a paralleldecoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decodingarchitectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)(2) single parity check turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10(-5) at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.
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