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A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems

JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2009年第1期69卷 1-11页

作者： Djamegni, Clementin Tayou Quinton, Patrice Rajopadhye, Sanjay Risset, Tanguy Tchuente, Maurice IRISA F-35042 Rennes France Colorado State Univ Ft Collins CO 80523 USA Univ Lyon INRIA INSA Lyon CITI F-69621 Villeurbanne France UR GEODES IRD F-93143 Bondy France

We address the problem of optimally mapping uniform DAGs to systolic arrays, given an affine timing function. We introduce an automatic allocation method based on a preprocessing by reindexing that transforms the initial DAG into a new one that enables the well known projection method to minimize the number of processors along a number of directions. We demonstrate its superiority to other methods. and establish the space-optimality of the proposed method. We also show an upper bound on the number of processors that corresponds to the best space complexity that both the projection method, and the so-called grouping method can give for the initial DAG. We also describe how the new allocation method can be implemented in tools. (C) 2008 Elsevier Inc. All rights reserved.

关键词： parallel embedded systems Timing function Timing surface Allocation function Space-optimality Space-time complexity Re-indexing Dependence graph Systolic arrays

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Design of a clock synchronisation sub-system for parallel embedded systems

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1997年第2期144卷 65-73页

作者： Fleury, M Downton, AC Clark, AF Sava, HP Laboratory of Chromatography DEPg.Fac.Quimica Universidad Nacional Autonoma de Mexico Circuito interior Cd Universitaria/CP 04510 Mexico D.F.Mexico

Software tools are being developed to support a design methodology specific to parallel real-time continuous-dataflow embedded systems. The authors describe the design of a global clock sub-system which is an essential component of an event trace tool. A new amalgam of algorithms is proposed which attends to the trade-off between clock accuracy and the need to restrict disturbance of the application whilst recording traces. The details of an implementation on a hybrid parallel processor, as well as the results of tracing applications in the given problem domain, are included.

关键词： clock synchronisation parallel embedded systems

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HEPSIM: an ESL HW/SW Co-Simulator/Analysis Tool for Heterogeneous parallel embedded systems 7

HEPSIM: an ESL HW/SW Co-Simulator/Analysis Tool for Heteroge...

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7th Mediterranean Conference on embedded Computing (MECO)

作者： Ciambrone, Daniele Muttillo, Vittoriano Pomante, Luigi Valente, Giacomo Univ Aquila Ctr Excellence DEWS Laquila Italy

ISBN: (纸本)9781538656839

Heterogeneous devices are becoming widely diffused in the embedded system domain, mainly because of the opportunities to increase application execution performance and, at the same time, to substantially reduce energy consumption. In such a context, this work faces the role of HW/SW co-simulators/analysis tools for embedded systems based on heterogeneous parallel architectures. In particular, it presents a SystemC-based tool for functional/timing HW/SW co-simulation and analysis within a reference ESL HW/SW co-design flow. The description of the main features of the tool, the main design and integration issues and an illustrative case study represent the core of the paper.

关键词： Electronic System-Level Design HW/SW Co-Design parallel embedded systems Heterogeneous systems

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Evaluation of the Impact of Miss Table and Victim Caches in parallel embedded systems

Evaluation of the Impact of Miss Table and Victim Caches in ...

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22nd International Conference on Microelectronics (ICM 2010)

作者： Asaduzzaman, Abu Mahgoub, Imad Sibai, Fadi N. Wichita State Univ Dept Elect Eng & Comp Sci Wichita KS 67260 USA Florida Atlantic Univ Dept Comp & Elect Engn & Comp Sci Boca Raton FL 33431 USA UAE Univ Fac IT Comp Syst Design Al Ain U Arab Emirates Wichita State Univ Wichita KS 67260 USA Florida Atlantic Univ Boca Raton FL 33431 USA UAE Univ Al Ain U Arab Emirates

ISBN: (纸本)9781612841519

parallel and distributed solutions are gaining increasing importance in designing embedded systems. Future parallel embedded systems are expected to have several hundred processing cores, improving the performance/power ratio. Multilevel caches in a multicore architecture require huge amount of power and may decrease processing speed due to cache's dynamic behavior. In this work, we investigate the impact of a Miss Table and victim caches at the cache level on performance and power consumption. The Miss Table holds information about the memory blocks those might cause more level-1 cache misses. Victim caches hold level-1 victim blocks. Cache locking algorithm and cache replacement scheme can directly be benefited by using the information stored in Miss Table and victim caches. We simulate a quad-core system with a two-level cache memory subsystem under MPEG4, H.264/AVC, FFT, and MI workloads. Experimental results show that the addition of the Miss Table and victim caches reduces the mean delay per task and the total power consumption by 32% and 41%, respectively.

关键词： Miss Table parallel embedded systems performance/power ratio victim cache

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Model-driven monitoring support for the multi-view performance analysis of parallel embedded applications

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PERFORMANCE EVALUATION 2000年第1-4期39卷 81-98页

作者： García, J Entrialgo, J Suárez, FJ García, DF Univ Oviedo Dept Informat Area Arquitectura & Tecnol Computadores Gijon 33204 Spain

This paper describes an approach to carry out performance analysis of parallel embedded applications. The approach is based on measurement, but in addition, the idea of driving the measurement process (application instrumentation and monitoring) by a behavioral model is introduced. Using this model, highly comprehensible performance information can be collected. The whole approach is based on this behavioral model, one instrumentation method and two tools, one for monitoring and the other for visualization and analysis. Each of these is briefly described, and the steps to carry out performance analysis using them are clearly defined. They are explained by means of a case study. Finally, one method to evaluate the intrusiveness of the monitoring approach is proposed, and the intrusiveness results for the case study are presented. (C)2000 Elsevier Science B.V. All rights reserved.

关键词： performance measurement performance visualization parallel embedded systems software instrumentation

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Efficient FPGA parallelization of Lipschitz Interpolation for Real-Time Decision-Making

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IEEE TRANSACTIONS ON CONTROL systems TECHNOLOGY 2022年第5期30卷 2163-2175页

作者： Nadales, J. M. Manzano, J. M. Barriga, A. Limon, D. Univ Seville Dept Automat Control & Syst Engn Seville 41004 Spain Univ Loyola Andalucia Dept Engn Dos Hermanas 41704 Spain Univ Seville Dept Elect & Electromagnetism Seville 41004 Spain

One of the main open challenges in the field of learning-based control is the design of computing architectures able to process data in an efficient way. This is of particular importance when time constraints must be met, as, for instance, in real-time decision-making systems operating at high frequencies or when a vast amount of data must be processed. In this respect, field-programmable gate array (FPGA)-based parallel processing architectures have been hailed as a potential solution to this problem. In this article, a low-level design methodology for the implementation on FPGA platforms of Lipschitz interpolation (LI) algorithms is presented. The proposed design procedure exploits the potential parallelism of the LI algorithm and allows the user to optimize the area and energy resources of the resulting implementation. Besides, the proposed design allows to know in advance a tight bound of the error committed by the FPGA due to the representation format. Therefore, the resulting implementation is a highly parallelized and a fast architecture with an optimal use of the resources and consumption and with a fixed numerical error bound. These facts flawlessly suit the desirable specifications of learning-based control devices. As an illustrative case study, the proposed algorithm and architecture have been used to learn a nonlinear model predictive control law applied to self-balance a two-wheel robot. The results show how computational times are several orders of magnitude reduced by employing the proposed parallel architecture, rather than sequentially running the algorithm on an embedded ARM-CPU-based platform.

关键词： Prediction algorithms Field programmable gate arrays Real-time systems parallel architectures Machine learning algorithms Interpolation Decision making Data-driven control field-programmable gate array (FPGA) implementation machine learning algorithms parallel embedded systems real-time control real-time decision-making

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Performance-steered design of software architectures for embedded multicore systems

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SOFTWARE-PRACTICE & EXPERIENCE 2002年第12期32卷 1155-1173页

作者： Bechini, A Prete, CA Univ Pisa Dipartimento Ingn Informaz I-56100 Pisa Italy

Many software applications demanding a considerable computing power are moving towards the field of embedded systems (and, in particular, hand-held devices). A possible way to increase the computing power of this kind of platform, so that both cost and power consumption are kept low, is the employment of multiple CPU cores on the same chipset. Consequently, it is essential to design applications that meet performance requirements leveraging the underlying parallel platform. As embedded applications are usually built using different components (whose source code is often not available) from different companies, the designer can mostly only operate at the architectural level. So far, methodologies for designing software architectures have mainly addressed general-purpose systems, often relying on hardware platforms with a high degree of parallelism. In this paper, we present our experience in architectural design of parallel embedded applications;as a result, we propose a possible methodology for the application design at the architectural level, targeted to embedded systems built upon multicore chipsets with a low degree of parallelism. It makes use of performance predictions, obtained by simulations. Such a methodology can be employed both for retargeting existing sequential applications to parallel processing platforms and for designing complete applications from scratch. We show the application of the proposed methodology to an embedded digital cartographic system. Starting with a software description using UML diagrams, candidate software architectures (utilizing different parallel solutions) are first defined and then evaluated, to end with the selection of the one yielding the highest performance gain. Copyright (C) 2002 John Wiley Sons, Ltd.

关键词： parallel embedded systems software architecture performance prediction digital cartography

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A GRASP for placement and routing of dataflow process networks on manycore architectures

A GRASP for placement and routing of dataflow process networ...

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8th International Conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Stan, Oana Sirdey, Renaud Carlier, Jacques Nace, Dritan CEA LIST Embedded Real Time Syst Lab Point Courrier 172 F-91191 Gif Sur Yvette France Univ Technol Compiegne CNRS UNR 6599 Heudiasyc F-60205 Compiegne France

ISBN: (纸本)9780769550947

We propose a GRASP heuristic for solving the joint problem of placement and routing of process networks from the field of compilation for embedded manycore architectures. The method we propose consists in assigning applications expressed as dataflow process networks on homogeneous manycore architectures by taking into account the routing maximal capacity of the arcs for the underlying Network-On-Chip. Our experiments illustrate the algorithm ability to efficiently obtain good quality routable assignments, within an acceptable computational time, even for large size instances. Moreover, validation of our approach is also realized on data coming from an embedded application of video processing.

关键词： parallel embedded systems dataflow compilation placement routing GRASP heuristic

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Constrained Mixed-Critical parallelization for Distributed Heterogeneous systems 9

Constrained Mixed-Critical Parallelization for Distributed H...

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9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing systems - Technology and Applications (IDAACS)

作者： Hoettger, Robert Oezcelikoers, Mustafa Heisig, Philipp Krawczyk, Lukas Wolff, Carsten Igel, Burkhard IDiAL Inst Dortmund Univ Appl Sci & Arts Dortmund Germany

ISBN: (纸本)9781538606971

Distributing software effectively to multi core, many core, and distributed systems has been studied for decades but still advances successively driven by domain specific constraints. Programming vehicle ECUs is one of the most constrained domains that recently approached the need for concurrency due to advanced driver assistant systems or autonomous driving approaches. In this paper, software distribution challenges for such systems are discussed and solutions are presented for instruction precise modeling, affinity constrained distribution, and reducing task response times achieved by advanced software parallelization. Therefore, existing partitioning and mapping algorithms are advanced to consider affinity constraints, software component tags and communication costs. Our experiments along a remote controlled model car show that using our new advanced results instead of sequential implementations or software distributions provided by the operating system on a distributed heterogeneous system significantly improves its responsiveness in order to potentially reduce energy consumption and replaces error prone manual constraint considerations for mixed-critical applications.

关键词： Constrained parallelization heterogeneous systems distributed systems multicore parallel embedded systems

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An embedded-processor architecture for parallel DSP algorithms 6

An embedded-processor architecture for parallel DSP algorith...

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Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations VI

作者： Hobson, RF Wong, PS Evenson, SA SIMON FRASER UNIV SCH COMP SCIBURNABYBC V5A 1S6CANADA

ISBN: (纸本)0819422347

A methodology for constructing parallel embedded DSP systems is described. The method uses a software and embedded processor abstraction to help raise the level of problem analysis above the raw state machine concept. Custom architectures are constructed by using multiple copies of a core embedded processor linked together with FIFO memories or other communication structures, and augmented with appropriate high speed data manipulation IO devices. Some field programmability and customization is possible through the use of SRAM program memories. © 1996 SPIE. All rights reserved.

关键词： parallel embedded systems custom DSP ATM User-Network Interfaces

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