This paper presents the results of an experimental study to evaluate the effectiveness of parallelsimulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper ...
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ISBN:
(纸本)9780818671203
This paper presents the results of an experimental study to evaluate the effectiveness of parallelsimulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-levelparallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuitsimulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.
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