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parallel logic simulation with assignable delays on a vector multiprocessor computer

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1997年第1期144卷 5-10页

作者： Jun, YH LG Semicon Co Ltd Dept Res & Dev 3 SeoCho Gu Seoul 137140 South Korea

The author presents a gate level high speed VLSI logic simulation algorithm with an assignable delay that uses bitwise logic operations, together with the segmented waveform relaxation method. Although the proposed technique has some similarity to the compiled code method, it does not generate a compiled code and can handle different delay models, a feature that the conventional compiled code method cannot handle. The proposed technique reduces the memory requirements and computation time by using segmented waveform relaxation, as well as the bitwise logic operations. In addition, the proposed algorithm can be easily implemented on a parallel computer and is structured to take full advantage of parallel processing. Implementation of the algorithm on a shared memory multiprocessor computer using eight processors (ALLIANT FX/8) shows a speedup of over 7 for combinational circuits, and can easily handle tens of thousands of gates.

关键词： parallel logic simulation vector multiprocessor computer

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parallel logic simulation on a network of workstations using a parallel virtual machine

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ACM Transactions on Design Automation of Electronic Systems 1997年第2期2卷 123-134页

作者： Kormicki, Maciek Mahmood, Ausif Carlson, Bradley S. Washington State University at Tri-Cities Richland WA United States University of Bridgeport Bridgeport CT United States State University of New York Stony Brook United States Computer Science and Engineering University of Bridgeport Bridgeport CT 06601 United States State University of New York at Stony Brook Stony Brook NY 11794-2350 United States

This paper explores parallel logic simulation on a network of workstations using a parallel virtual machine (PVM). A novel parallel implementation of the centralized-time event-driven logic simulation algorithm is carried out such that no global controlling workstation is needed to synchronize the advance of simulation time. Further advantages of our new approach include a random partitioning of the circuit onto available workstations and a pipelined execution of the different phases of the simulation algorithm. To achieve a better load balance, we employ a semioptimistic scheme for gate evaluations (in conjunction with a centralized-time algorithm) such that no rollback is required. The performance of this implementation has been evaluated using the ISCAS benchmark circuits. Speedups improve with the size of the circuit and the activity level in the circuit. Analyses of the communication overhead show that the techniques developed here will yield even higher gains as newer networking technologies like ATM are employed to connect workstations. © 1997 ACM.

关键词： Distributed computing parallel logic simulation PVM Synchronous simulation

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Concurrency preserving partitioning algorithm for parallel logic simulation

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VLSI DESIGN 1999年第3期9卷 253-270页

作者： Kim, HK Jean, J Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA

A partitioning algorithm for parallel discrete event gate-level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases and three conflicting goals can be separately considered so to reduce computational complexity. To evaluate the quality of partitioning algorithms in terms of preserving concurrency, a concurrency metric that requires neither sequential nor parallel simulation is proposed. A levelization technique is used in computing the metric so to determine gates which can be evaluated at about the same time. A parallel gate-level logic simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the performance of the iCPP algorithm. The results are compared with several other partitioning algorithms to show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

关键词： parallel logic simulation partitioning algorithm discrete event simulation concurrency load balancing time warp

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EXPERIMENTAL EVALUATION OF DYNAMIC SCHEDULING FOR parallel logic simulation USING BENCHMARK CIRCUITS

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第11期E77A卷 1910-1912页

作者： SEKO, T KIKUNO, T Nara Natl Coll of Technology Yamatokoriyama-shi Japan

We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time-first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well-known twelve benchmark combinational circuits show the usefulness of Algorithm MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.

关键词： parallel logic simulation PROCESSOR SCHEDULING

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GPU-based Hybrid parallel logic simulation for Scan Patterns 4

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns

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4th IEEE International Test Conference in Asia (ITC-Asia)

作者： Lai, Liyang Zhang, Qiting Tsai, Hans Cheng, Wu-Tung Shantou Univ Key Lab Intelligent Mfg Technol Guangdong Prov Key Lab Digital Signal & Image Pro Minist Educ Elect Engn Shantou Guangdong Peoples R China Mentor Wilsonville OR USA

ISBN: (纸本)9781728189444

GPGPU, general-purpose computing on graphics processing units, has been witnessed growing from a niche to a mainstream computing paradigm in the last decade. It is widely deployed in machine learning, artificial intelligence, and many scientific applications. In this article, we study gate-level logic simulation for scan test patterns, one of the key algorithmic components for test generation, fault grading and design rule check. We are exploring if GPGPU can deliver scalable performance speedup as promised by its massive parallelism. We discuss the limitations of the state of art work. With GPUs' architectural features in mind, a novel algorithm of hybrid race-tolerant parallel logic simulation is proposed to unleash its immense power of parallelization. Its unique integration of oblivious simulation and event-driven simulation leads to a scalable realization of parallel logic simulation for scan patterns. For the first time in the literature, it is demonstrated that a modest GPU can handle an industrial design of over twenty million gates with excellent performance scalability.

关键词： event-driven simulation GPGPU oblivious simulation parallel logic simulation

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An improved F-M partitioning algorithm in parallel logic simulation

An improved F-M partitioning algorithm in parallel logic sim...

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2010 International Colloquium on Computing,Communication, Control, and Management (CCCM2010)

作者： Jiafang Wang School of Computer Science and Technology Heilongjiang University Harbin,China Yuzhuo Fu School of Microelectronics Shanghai Jiaotong University Shanghai,China

The increasing complexity of digital VLSI designs is causing the simulation execution time to increase enormously. Circuit partitioning is an efficient way to speed up the parallel simulation and reduce the communication *** on classical F-M heuristic algorithm,we proposed a multilevel partitioning approach TCFM,which can get fast convergence of F-M algorithm by refining the initial *** simulator was implemented on Network of workstations and a benchmark of ISCAS85 was executed to show that it is feasible to obtain the speedup and lower communication overhead.

关键词： F-M heuristic algorithm Synchronization parallel logic simulation Discovery Multilevel Partitioning

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Concurrency preserving partitioning (CPP) for parallel logic simulation 96

Concurrency preserving partitioning (CPP) for parallel logic...

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Proceedings of the tenth workshop on parallel and distributed simulation

作者： Hong K. Kim Jack Jean Department of Computer Science and Engineering Wright State University Dayton Ohio

ISBN: (纸本)9780818675393

Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.

关键词： Load Balancing parallel logic simulation Partitioning Concurrency Time Warp

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An Novel F-M Partitioning Algorithm for parallel logic simulation

An Novel F-M Partitioning Algorithm for Parallel Logic Simul...

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The second International Conference of Electrical and Electronics Engineering(ICEEE 2011)

作者： Wang Jiafang Fu Yuzhuo School of Computer Science Harbin Engineering University School of Computer Science and Technology Heilongjiang University Schoold of Microelectronics Shanghai Jiao tong University

The increasing complexity of digital VLSI designs caused the simulation execution time to increase enormouslyCircuit partitioning is an efficient way to speed up the parallel simulation and reduce the communication overheadBased on classical F-M heuristic algorithm, we proposed a multilevel partitioning approach TCFM, which can get fast convergence of F-M algorithm by refining the initial partitioningThe simulator was implemented on Network of workstations and a benchmark of ISCAS85 was executed to show that TCFM is feasible to obtain the speedup and lower communication overhead.

关键词： F-M heuristic algorithm synchronization parallel logic simulation Discovery multilevel partitioning

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An Improved F-M Partitioning Algorithm in parallel logic simulation

An Improved F-M Partitioning Algorithm in Parallel Logic Sim...

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The 2011 Fourth International Symposium on Knowledge Acquisition and Modeling（KAM 2011）

作者： Jiafang Wang Yuzhuo Fu School of Computer Science and Technology Heilongjiang University School of Microelectronics Shanghai Jiaotong University

The increasing complexity of digital VLSI designs is causing the simulation execution time to increase enormously. Circuit partitioning is an efficient way to speed up the parallel simulation and reduce the communication overhead. Based on classical F-M heuristic algorithm, we proposed a multilevel partitioning approach TCFM, which can get fast convergence of F-M algorithm by refining the initial partitioning. The simulator was implemented on Network of workstations and a benchmark of ISCAS85 was executed to show that it is feasible to obtain the speedup and lower communication overhead.

关键词： F-M heuristic algorithm Synchronization parallel logic simulation Discovery Multilevel Partitioning

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parallel event-driven logic simulation algorithms: Tutorial and comparative evaluation

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1996年第4期143卷 177-185页

作者： Baker, WI Mahmood, A Carlson, BS UNIV BRIDGEPORT BRIDGEPORTCT 06601 SUNY STONY BROOK STONY BROOKNY 11794

parallel processing offers a viable way to improve the enormous execution time of the simulation of large VLSI designs. Various parallel logic simulation approaches have been proposed in recent years resulting in some ambiguity as to the best parallelism and address these issues, the authors provide a detailed comparison of all four major types of event-driven logic simulation algorithms (synchronous, conservative asynchronous with deadlock avoidance, conservative asynchronous with deadlock detection and resolution, and optimistic asynchronous). The comparisons are carried out on an ideal parallel machine capable of extracting all available parallelism in a given algorithm. The simulation execution time, average parallelism and total messages required for a particular simulation algorithm are measured on the ISCAS combinational and sequential benchmark circuits. The use of an ideal parallel machine exposes characteristics of the simulation algorithms independent of the effects caused by particular parallel architectures or implementations. It is shown that a recently developed conservative asynchronous algorithm of the deadlock avoidance type and the optimistic asynchronous algorithm achieve the best parallel execution time results. However, the new conservative algorithm requires much less implementation overhead than the optimistic algorithm.

关键词： parallel logic simulation event-driven simulation synchronous simulation asynchronous simulation distributed simulation simulation

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