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IEEE/ACIS 21st International Fall Virtual Conference on Computer and Information Science (ICIS Fall)

作者： Jia, Shiwei Tian, Ze Ma, Yueyuan Sun, Chenglu Zhang, Yimen Zhang, Yuming Xidian Univ Sch Microelect Xian Peoples R China China Aeronaut Comp Res Inst Microelect Res Lab Xian Peoples R China Queens Univ Sch Chem Belfast Antrim North Ireland Xiangteng Microelect Corp Dept Integrated Circuit R&D Xian Peoples R China

ISBN: (纸本)9781728176796

General purpose graphic processor unit (GPGPU) supports various applications' execution in different fields with high-performance computing capability due to its powerful parallel processing architecture. However, GPGPU parallel processing architecture also has the "memory wall" issue. When memory access in application is intensive or irregular, memory resource competition occurs and then degrade the performance of memory system. In addition, with multithreads' requirement for different on-chip resources such as register and warp slot being inconsistant, as well as the branch divergence irregular computing applications, the development of thread level parallelism (TLP) is severely restrited. Due to the restrictions of memory access and TLP, the acceleration capability of GPGPU large-scale parallel processing architecture has not been developed effectively. Alleviating memory resource contention and improving TLP is the performance optimization hotspot for current GPGPU architecture. In this paper we research how memory access optimization and TLP improvement could contribute to the optimization of parallel processing architecture performance. First we find that memory access optimization could be accomplished by three ways: reducing the number of global memory access, improving memory access latency hiding capability and optimizing cache subsystem performance. Then in order to improve TLP, optimizing thread allocation scheme, developing data approximation and redundancy, as well as compacting branch divergence, researches of these three aspects are surveyed. We also analyze the working mechanism, advantages and challenges of each research. At the end, we suggest the direction of future GPGPU parallel processing architecture optimization.

关键词： GPGPU parallel processing architecture thread level parallelism memory system performance

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A Fast and Scalable FPGA-Based parallel processing architecture for K-Means Clustering for Big Data Analysis

A Fast and Scalable FPGA-Based Parallel Processing Architect...

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IEEE Pacific Rim Conference on Communications, Computers and Signal processing (PACRIM)

作者： Raghavan, Ramprasad Perera, Darshika G. Univ Colorado Dept Elect & Comp Engn Colorado Springs CO 80933 USA

ISBN: (纸本)9781538607008

The exponential growth of complex, heterogeneous, dynamic, and unbounded data, generated by a variety of fields including health, genomics, physics, climatology, and social networks pose significant challenges in data processing and desired speed-performance. Existing processor-based software-only algorithms are incapable of analyzing and processing this enormous amount of data, efficiently and effectively. Consequently, some kind of hardware support is desirable to overcome the challenges in analyzing big data. Big data analytics involves many important data mining tasks including clustering, which categorizes the data into meaningful groups based on the similarity or dissimilarity among objects. In this research work, we introduce an efficient FPGA-based parallel processing architecture for K-means Clustering, one of the most popular clustering algorithms. Experiments are performed on a benchmark dataset to evaluate the feasibility and efficiency of our hardware design. Our hardware architecture is generic, parameterized, and scalable to support larger and varying datasets as well as a varying number of clusters. Our hardware configuration with 32 processing elements (PEs) achieved 368 times speedup compared to its software counterpart.

关键词： Big data analysis parallel processing architecture FPGAs K-Means clustering embedded hardware hardware algorithms data mining

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AN OPTIMUM parallel architecture FOR HIGH-SPEED REAL-TIME DIGITAL SIGNAL-processing

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COMPUTER 1988年第2期21卷 47-57页

作者： LANG, GR DHARSSI, M LONGSTAFF, FM LONGSTAFF, PS METFORD, PAS RIMMER, MT MOTOROLA INFORMAT SYST RES & DEV9445 AIRPORT RDBRAMPTON L6S 4J3ONTARIOCANADA MOTOROLA INFORMAT SYST SYST & SOFTWARE DEVBRAMPTON L6S 4J3ONTARIOCANADA

The authors describe a parallel processing architecture for real-time digital signal processing that has demonstrated virtually 100% data processing efficiency in a number of areas. The Teamed-architecture Signal Processor (T-ASP) is a field-proven, commercially available optimal system solution to the extremely high computational and I/O rates encountered in modern digital-signal-processing environments. The design of T-ASP involves the consideration and implementation of many architectural concepts used to enhance the performance of a computer, including programmability, parallel processing, vector processing and pipelining, memory interleaving, double cache memories, multiple high-speed I/O interfaces, and segmentation of the processors for elimination of both CPU and data-handling overhead. The authors discuss hardware architecture design and implementation; hardware management; and software architecture design and implementation.

关键词： CPU I/O rates Teamed-architecture Signal Processor computerised signal processing data-handling double cache memories hardware management high-speed real-time digital signal processing memory interleaving multiple high-speed I/O interfaces optimum parallel architecture parallel architectures parallel machines parallel processing parallel processing architecture pipelining programmability real-time systems software architecture design vector processing

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A Full-Featured FPGA-Based Pipelined architecture for SIFT Extraction

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IEEE ACCESS 2021年 9卷 128564-128573页

作者： Kreowsky, Philipp Stabernack, Benno Heinrich Hertz Inst Nachrichtentech Berlin GmbH Fraunhofer Inst Telecommun D-10587 Berlin Germany Univ Potsdam Embedded Syst Architectures Signal Proc D-14469 Potsdam Germany

Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.

关键词： Field programmable gate arrays Convolution Signal processing algorithms Kernel Image resolution Histograms Feature extraction Scale-invariant feature transform (SIFT) field-programmable gate array (FPGA) image processing computer vision parallel processing architecture real-time hardware architecture

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A high performance switch for OC-12 SONET self-healing ring networks

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1996年第2期14卷 353-361页

作者： Takatori, M Nakano, Y Ashi, Y Fujita, H Mizukami, M Itoh, K HITACHI LTD DEV DIVICE CTRTOKYO 198JAPAN HITACHI COMMUN SYST INC KANAGAWA 244JAPAN

The progress of ITU-T and ANSI standards on SDH/SONET is accelerating the evolution of transmission systems all over the world. The advanced operation administration and maintenance (OAM) functions it provides makes it possible to create a self-healing ring network which protects against failure. This self-healing ring consists of add/drop multiplexers (ADM's). The switch in the ADM plays an important role in achieving self-healing operation. In this paper, self-healing ring architecture and operations are analyzed in order to determine the requirements for the ADM switch. On the basis of this result, new space division switching methods, which significantly reduce the amount of hardware needed, are proposed, A parallel processing architecture which makes it possible to develop a low-cost large-scale switch is also devised, Finally, a developed switch LSI chip is presented. Combining two identical chips with the proposed parallel processing architecture, a 32 x 32 STS-3 switch (5 Gb/s throughput) with an STS-1 time slot interchange (TSI) function is realized.

关键词： Transmission systems Computer hardware Switches ANSI standards parallel processing architecture Ring networks space division SONET

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Experimental systems implementation of a hybrid optical-digital correlator

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APPLIED OPTICS 1999年第29期38卷 6116-6128页

作者： Sharp, JH MacKay, NE Tang, PC Watson, IA Scott, BF Budgett, DM Chatwin, CR Young, RCD Tonda, S Huignard, JP Slack, TG Collings, N Pourzand, AR Duelli, M Grattarola, A Braccini, C Univ Sussex Sch Engn Brighton BN1 9Q2 E Sussex England Thomson CSF Cent Rech Lab F-91404 Orsay France British Aerosp Operat Ltd Sowerby Res Ctr Dept Opt & Laser Technol Bristol BS12 7QW Avon England Univ Neuchatel Inst Microtechnol CH-2000 Neuchatel Switzerland Univ Genoa Dept Commun Comp & Syst Sci I-16145 Genoa Italy Univ Glasgow Dept Mech Engn Laser & Opt Syst Engn Ctr Glasgow G12 8QQ Lanark Scotland

A high-speed hybrid optical-digital correlator system was designed, constructed, modeled, and demonstrated experimentally. This correlator is capable of operation at approximately 3000 correlations/s. The input scene is digitized at a resolution of 512 x 512 pixels and the phase information of the two-dimensional fast Fourier transform calculated and displayed in the correlator filter plane at normal video frame rates. High-fidelity reference template images are stored in a phase-conjugating optical memory placed at the nominal input plane of the correlator and reconstructed with a high-speed acousto-optic scanner;this allows for cross correlation of the entire reference data set with the input scene within one frame period. A high-speed CCD camera is used to capture the correlation-plane image, and rapid correlation-plane processing is achieved with a parallel processing architecture. (C) 1999 Optical Society of America.

关键词： two-dimensional Fourier transform Cross correlation Charge Coupled Device camera frame period Optical data storage parallel processing architecture Planing Phase high fidelity VIDEO FRAMES Fast Fourier transform

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Design and implementation of parallel video combiner architecture for multi-user video conferencing at ultra-high definition resolution

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MULTIMEDIA TOOLS AND APPLICATIONS 2015年第17期74卷 6589-6622页

作者： Baskaran, Vishnu Monn Chang, Yoong Choon Loo, Jonathan Wong, KokSheik Multimedia Univ Fac Engn Persiaran Multimedia Cyberjaya 63100 Selangor Malaysia Middlesex Univ Sch Sci & Technol London NW4 4BT England Univ Malaya Fac Comp Sci & Informat Technol Kuala Lumpur 50603 Malaysia

In software driven multi-user video conferencing systems, consumer progression towards ultra-high definition (i.e., 8 k) resolution introduces new challenges to the video combination process in sustaining smooth combined video playback at high frame rates. As such, this paper analyzes the underlying architecture of a conventional video combiner to identify the performance impact of combined video frame rates at ultra-high definition resolutions. Then, two straightforward parallel video combination architectures using software application threads, namely PVC-1 and PVC-2, are studied as a benchmark. In PVC-1, the number of application threads tallies with the number of client videos to be combined, which improves playback performance at the expense of inconsistencies in inset client frame rates within a combined video. PVC-2 includes a synchronizer to address these inconsistencies, but exhibits marginal performance gains. To address the aforementioned problems, a balanced workload parallel video combiner architecture is proposed, namely PVC-3. In this architecture, a balanced workload management algorithm stitches client videos into an ultra-high definition combined frame, based on the number of available logical processors on a multi-core processor. This method improves frame rate performance and sustains consistent client frame rates within a combined video. Experimental results suggest that PVC-3 is superior over PVC-2 and achieves a frame rate performance gain of 27 % against a conventional video combiner for a combined video of 16 clients (each at a resolution of 720p) and zero standard deviation in combined frame rate consistency.

关键词： Video combiner parallel processing architecture Balanced workload Multi-user video conferencing Ultra-high definition resolution

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FPGA-Based Hardware Design for Scale-Invariant Feature Transform

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IEEE ACCESS 2018年 6卷 43850-43864页

作者： Li, Shih-An Wang, Wei-Yen Pan, Wei-Zheng Hsu, Chen-Chien James Lu, Cheng-Kai Tamkang Univ Dept Elect Engn New Taipei 25137 Taiwan Natl Taiwan Normal Univ Dept Elect Engn Taipei 10610 Taiwan Univ Teknol PETRONAS Dept Elect & Elect Engn Bandar Seri Iskandar 32610 Malaysia

This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.

关键词： Scale-invariant feature transform field-programmable gate array parallel processing architecture

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Exploration of Efficient Many-Core Processor for Dual-Polarization and Sympathetic Plucked String Model

Exploration of Efficient Many-Core Processor for Dual-Polari...

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5th International Conference on Information Science and Applications (ICISA)

作者： Kang, Myeongsu Kim, Jong-Myon Univ Ulsan Dept Elect Engn Ulsan 680749 South Korea

ISBN: (纸本)9781479944415

Despite the fact that physics-based sound synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research on parallel processing architectures that support the physics-based sound synthesis of musical instruments. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, this paper explores a many-core processor for varying its PE configurations. To find the optimal PE configuration, each PE configuration is evaluated in terms of execution time, system power, and area. Experimental results indicate that the most efficient operation in order to synthesize 44,100 six-note polyphonic acoustic guitar sound sampled at 44.1 kHz is achieved as the number of PEs equals to 192. Likewise, all PE configurations used in this study are satisfied with the system requirements to implement sound synthesis on a portable device.

关键词： Design space exploration Many-core processor parallel processing architecture Physics-based sound synthesis

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Detection of temporarily static regions by processing video at different frame rates

Detection of temporarily static regions by processing video ...

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IEEE Conference on Advanced Video and Signal Based Surveillance

作者： Porikli, Fatih Mitsubishi Electric Research Laboratories (MERL) Cambridge United States

ISBN: (纸本)9781424416950

This paper presents an abandoned item and illegally parked vehicle detection method for single static camera video surveillance applications. By processing the input video at different frame rates, two backgrounds are constructed, one for short-term and another for long-term. Each of these backgrounds is defined as a mixture of Gaussian models, which are adapted using online Bayesian update. Two binary foreground maps are estimated by comparing the current frame with the backgrounds, and motion statistics are aggregated in a likelihood image by applying a set of heuristics to the foreground maps. Likelihood image is then used to differentiate between the pixels that belong to moving objects, temporarily static regions and scene background. Depending on the application, the temporary static regions indicate abandoned items, illegally parked vehicles, objects removed from the scene, etc. The presented pixel-wise method does not require object tracking, thus its performance is not upper-bounded to error prone detection and correspondence tasks that usually fail for crowded scenes. It accurately segments objects even if they are fully occluded. It can also be effectively implemented on a parallel processing architecture.

关键词： Frame Rate Videotapes parallel processing architecture Heuristics pixel

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