The potential of parallel processing architecture is evaluated for power oscillation monitoring. In the emerging smart grid architecture using Wide Area Monitoring System (WAMS), data collected from Phasor Measurement...
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ISBN:
(纸本)9781424468904
The potential of parallel processing architecture is evaluated for power oscillation monitoring. In the emerging smart grid architecture using Wide Area Monitoring System (WAMS), data collected from Phasor Measurement Units (PMU) in remote locations are transmitted in real-time to the control center. The power system network oscillatory dynamic behavior can then be extracted online using modern signal processing techniques. In this paper an Extended Complex Kalman Filter (ECKF) algorithm is adopted for tracking oscillations. A brief overview of this method along with background of WAMS is presented. Later, parallelism is achieved by decomposing ECKF method into a set of subroutines and distributing them across multiple CPU cores. Comparisons of this performance with a conventional sequential structure is conducted using synthetic signals in MATLAB and Visual C++. The simulation results show that parallelprocessing is able to reduce the computing time.
Network Function Virtualization (NFV) provides great flexibility in solving the problem of deploying service function chains (SFCs). The existing serial SFCs organize virtual network functions (VNFs) in a predefined o...
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Network Function Virtualization (NFV) provides great flexibility in solving the problem of deploying service function chains (SFCs). The existing serial SFCs organize virtual network functions (VNFs) in a predefined order and execute the VNFs one by one, which can result in high SFC delay as the lengths of the SFCs increases. In order to address this problem, in this work, the SFC parallelization is adopted to accelerate the SFCs. Furthermore, a heuristic algorithm is proposed to solve the problem of deploying parallelized SFCs. Specifically, a distributed NFV architecture is used to implement parallelized SFCs, and an effective algorithm is developed to parallelize serial SFCs based on the VNF dependency. Further, a heuristic algorithm is proposed to deploy the parallelized SFCs onto a distributed network with the objective to minimize the average SFC delay. The simulation results show that the proposed algorithm can significantly reduce the SFC delay, increase the utilization efficiency of node resources, and obtain a high acceptance rate of user requests.
The primary display technology utilized by today's printers is halftoning image, and among the various image halftoning methods that are currently being used, Direct Binary Search (DBS) is the method that produces...
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The primary display technology utilized by today's printers is halftoning image, and among the various image halftoning methods that are currently being used, Direct Binary Search (DBS) is the method that produces the best image quality. However, one disadvantage of this method is the requirement that images be constantly iterated, as this places many limitations on the method with respect to processing speed. In view of this issue, this work proposes an effective hardware architecture design for the DBS method that would allow for image quality to be maintained and for real-time processing to be carried out. The study proposes the application of the line buffer method to the Very Large Scale Integration (VLSI) process, so as to reduce memory usage, enable the use of a parallel processing architecture. Thus, increase the speed of the process. As results, the DBS halftoning image method was used on a gray image, and it was found that, with respect to the image, the number of iterations used and the halftone image values generated by the hardware that was updated based on the visual model error table were consistent with the results generated by software algorithms.
This paper introduces an effective parallelprocessing method to design the on-board SAR (Synthetic Aperture Radar) real time imaging processor using FPGA+DSP based on the high-resolution imaging algorithm. The archit...
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ISBN:
(数字)9781728123455
ISBN:
(纸本)9781728123462
This paper introduces an effective parallelprocessing method to design the on-board SAR (Synthetic Aperture Radar) real time imaging processor using FPGA+DSP based on the high-resolution imaging algorithm. The architecture of this processor is designed based on the analysis of the algorithm operation characteristics and the inherent time relationship. In order to reduce the time consumption, pipeline and parallel joint processing method is applied. In addition, the system uses a combination of floating-point operations and fixed-point operations, which not only meets the imaging accuracy requirements but also saves the hardware scale of the system. The system requires 24s to focus the GF-3 stripmap SAR raw data with a granularity of 16384*16384 when works in 100MHz. The results demonstrate that our method was effective and the imaging quality can meet the requirements.
In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute memory expl...
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ISBN:
(纸本)9781479928941
In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute memory exploits the relaxed precision and linearity requirements of pattern recognition applications. System-level simulations incorporating various deterministic errors from analog signal chain demonstrates the limited accuracy of analog processing does not significantly degrade the system performance, which means the probability of pattern detection is minimally impacted. The estimated energy saving is 63 % as compared to the conventional system with standard embedded memory and parallel processing architecture, for 256×256 target image.
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