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Low-energy Pipelined Hardware Design for Approximate Medium Filter

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC systemS 2023年第3期28卷 1-21页

作者： Mahmoud, Mervat M. A. Elashkar, Nahla E. Draz, Heba H. Elect Res Inst Microelect Dept Cairo Egypt British Univ Egypt Dept Elect Engn Cairo Egypt

Image and video processing algorithms are currently crucial for many applications. Hardware implementation of these algorithms provides higher speed for large computation applications. Removing noise is often a typical pre-processing step to enhance the results of later analysis and processing. Median filter is a typical nonlinear filter that is very commonly used for impulse noise elimination in digital image processing. This article suggests a low-energy median filter hardware design for battery-based hardware applications. An approximate solution with high accuracy is investigated to speed up the filtering operation, reduce the area, and consume less power/energy. Pipelining and parallelism are used to optimize the speed and power of this technique. Non-pipelined, two different pipelined structures, and two parallel architectures versions are designed. The design versions are implemented first with a Virtex-5 LX110T FPGA and then using the UMC 130nm standard cell ASIC technology. The selection and the even-odd sorting-based median filters are also implemented for an equitable comparison with the standard median filtering techniques. The suggested non-pipelined median filter design enhances the throughput 35% more than the highest investigated state of the art. The pipelining enhances the throughput to more than twice its value. Additionally, the parallel architecture decreases the area and the consumed power by around 40%. The simulation results reveal that one of the suggested designs significantly decreases the area, with the same speed as the fastest design in the literature, without noticeably degrading the accuracy, and a significant decrease in energy consumption by about 60%.

关键词： Application specific integrated circuits (ASIC) field programmable gate arrays (FPGA) hardware accelerator image denoising median filter parallel processing system

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Design of a parallel processing system Based on DSP

Design of a Parallel Processing System Based on DSP

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ICEMI'2005第七届国际电子测量与仪器学术会议

作者： Xiong Xia Wu Ying Hu Wendi (Institute of Information Engineering, Information Engineering University, Zhengzhou 450002 China)

In this paper, we put forward an application of the parallel structure in the multi-beam system for satellite detection and control. The basic elements of parallel system: processing unit, parallel pr

关键词： parallel processing system algorithm direction of arrive(DOA) beamforming.

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An MAMS-PP4: Multi-access memory system used to improve the processing speed of visual media applications in a parallel processing system\

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2004年第11期E87A卷 2852-2858页

作者： Lee, H Cho, HK You, DS Park, JW Daejeon Hlth Sci Coll Taejon South Korea Chungnam Natl Univ Chungnam South Korea

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD) architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 x pq), a vertical (pq x 1) or a block (p x q) subarray with a constant interval in an arbitrary position in an M x N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD) computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

关键词： visual media processing parallel processing system multiaccess memory system SIMD

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Micro-Task processing in Heterogeneous Reconfigurable systems

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Journal of Computer Science & Technology 2005年第5期20卷 624-634页

作者： Sebastian Wallner Department of Distributed Systems Technical University of Hamburg-Harburg Schwarzenbergstrasse 95 D-21073 Hambur9 Germany

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable system-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

关键词： system-on-chip reconfigurable heterogeneous architectures configuration instructions descriptors parallel processing system signal processing

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Micro-task processing in heterogeneous reconfigurable systems

Micro-task processing in heterogeneous reconfigurable system...

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9th Asia-Pacific Computer systems Architecture Conference (ACSAC 2004)

作者： Wallner, S Tech Univ Hamburg Dept Distributed Syst D-21073 Hamburg Germany

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable system-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

关键词： system-on-chip reconfigurable heterogeneous architectures configuration instructions descriptors parallel processing system signal processing

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Reconfigurable free-space optical interconnection module for pipelined optoelectronic parallel processing

Reconfigurable free-space optical interconnection module for...

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Conference on Spatial Light Modulators

作者： Ishikawa, M Naruse, M Goulet, A Toyoda, H Kobayashi, Y Univ Tokyo Grad Sch Informat Sci & Technol Dept Informat Phys & Comp Bunkyo Ku Tokyo 1130033 Japan

ISBN: (纸本)0819441716

Optical interconnections and integrated optoelectronic devices are expected to be promising candidates that expand interconnection bandwidth between large-scale integrated circuits (LSIs). We have constructed an optoelectronic parallel computing system that has a reconfigurable free-space parallel optical interconnection module called OCULAR-II. It has a multi-layer architecture that eliminates the data transfer bottleneck between optoelectronic processing modules by reconfigurable free-space optical interconnections. An optoelectronic processing module is composed of a two-dimensional processing element array where each pixel has its own optical output channel by a VCSEL and optical input channel. The optical interconnection is integrated into a compact module where an optically addressable phase only spatial light modulator and an imaging optical system are compactly fabricated. Each component of the OCULAR-II system has been designed to be modular and compact. Therefore, just cascading optoelectronic processing modules and optical interconnection modules makes a pipelined parallel processing system. In the optical interconnection module, a custom designed Fourier Transform lens has been used to reduce the working distance of the lens system. A Computer Generated Hologram (CGH) is written on a liquid crystal display (LCD) that is coupled by a fiber optic plate (FOP) to the optically addressable SLM. The interconnection topology between optoelectronic chips is controlled by changing the CGH patterns, which is calculated in advance. A global interconnectivity among processor arrays is also achievable since the communication channels are constructed via optical path in free-space. The data broadcasting between processors that are located spatially far away can be efficiently implemented by free-space optical links in OCULAR-II's optical interconnection module.

关键词： optical interconnection spatial light modulator reconfigurable optical interconnection parallel processing system pipeline architecture

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Performance Evaluation of Dynamic Sharing of Processors in Two-Stage parallel processing systems

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IEEE Transactions on parallel and Distributed systems 1993年第3期4卷 306-317页

作者： Huang, Jau-Hsiung Kleinrock, Leonard Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan Computer Science Departmen University of California Los Angeles CA 90024 United States

In this paper, we first study the performance of job scheduling in a large parallel processing system where a job is modeled as a concatenation of two stages which must be processed in sequence. We denote Pi as the number of processors required by stage i and denote P as the total number of processors in the system. The service time requirement of stage i, given the required Pi processors, is exponentially distributed with mean 1/μ_i. Hence, a job can be fully described by a quadruple (P₁, P₂, μ₁, μ₂). Three service disciplines which can fully utilize all processors in the system are studied in this paper. We first consider a large parallel computing system where Max(P₁.P₂) > P Ӳ 1 and Max(P₁, P₂) Ӳ Min(P₁.P₂). For such systems, exact expressions for the mean system delay are obtained for various job models and disciplines. Our results show that the priority should be given to jobs working on the stage which requires fewer processors. We then relax the large parallel system (i.e., P Ӳ 1) condition to obtain the mean system time for two job models when the priority is given to the second stage. Moreover, a Scale-up Rule is introduced to obtain the approximated delay performance when the system provides more processors than the maximum number of processors required by both stages (i.e., P > Max(P₁.P₂)). Lastly, an approximation model is given for jobs with more than two stages. © 1993 IEEE

关键词： High-concurrency stage low-concurrency stage parallel processing system processor sharing Scale-up rule

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CLIP-4 parallel processing system

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1980年第5期127卷 219-224页

作者： FOUNTAIN, TJ GOETCHERIAN, V LOGICA LTD LONDON W1A 4SEENGLAND

A machine, Clip 4, is described, which is based on the ideas of parallel image processing developed at University College London. The major sections of the machine are outlined, including the processor array, which comprises 1152 custom-designed integrated circuits. A programming language has been developed and the application of the hardware/software system to a number of image-processing problems is shown. The processing speed of the system is indicated, and is typically several orders of magnitude better than moderately sized mainframe serial computers.

关键词： image processing parallel processing system Mainframes and minicomputers Clip 4 computerised picture processing Communications computing parallel processing

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