In this paper, we concentrate on the scheduling problem with interruption occurs in the parallel processor system. The situation happens when the availability of the unrelated parallelprocessors in the time slot decr...
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ISBN:
(纸本)9780735412415
In this paper, we concentrate on the scheduling problem with interruption occurs in the parallel processor system. The situation happens when the availability of the unrelated parallelprocessors in the time slot decreases in certain time periods and its define as resource disruption. Our objective is to consider a recovery scheduling option for this issue to overcome the possibilities of having infeasibility of the original scheduling plan. Our approach for the recovery is task rescheduling which is to assign the tasks in the initial schedule plan to reflect the new restrictions. A recovery mixed integer linear programming model is proposed to solve the disruption problem. We also conduct a computational experiment using CPLEX 12.1 solver in AIMMS 3.10 software to analyze the performance of the model.
We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without...
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We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1.5 mu m CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.
We have designed a parallel processor system with hundreds of processors specific for Monte- Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system acco...
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ISBN:
(纸本)0819417475
We have designed a parallel processor system with hundreds of processors specific for Monte- Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose introducing the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring- bus. It was confirmed in simulation that the optical data transfer operation and the memory store operation into FIFO in the optical ring-bus interface unit can be successfully performed.
Human Genome Analysis and Image Processing are part of the 'Grand Challenges' in High Performance Computing. The traditional mainframe has become insufficient for these applications in Biocomputing. New scalab...
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Human Genome Analysis and Image Processing are part of the 'Grand Challenges' in High Performance Computing. The traditional mainframe has become insufficient for these applications in Biocomputing. New scalable parallel processor systems enter the marketplace with superior price/performance. The evaluation process of such a system by an application-oriented benchmark test suite is described. The system is integrated in the client/server structure of the Deutsches Krebsforschungszentrum where 'rightsizing' will eliminate the mainframe completely in the near future.
We have proposed a new three-dimensional optically coupled common memory (3D-OCC memory) to solve the problem of bus bottle neck in the multi-processorsystem with the shared memories. Three-dimensional-OCC memory con...
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ISBN:
(纸本)0819417475
We have proposed a new three-dimensional optically coupled common memory (3D-OCC memory) to solve the problem of bus bottle neck in the multi-processorsystem with the shared memories. Three-dimensional-OCC memory consists of several memory layers vertically stacked and a block of data is simultaneously transferred among these memories using vertically optical interconnection. Three-dimensional-OCC memory acts as the real shared memory. Three-dimensional-OCC memory test chip has been fabricated using 2 micrometers CMOS technology. LEDs are integrated on the silicon test chip by using a newly developed micro-bonding technology. We observed the uniform photon emission from these LEDs. In addition, the basic operation of 3D-OCC memory for optical writing/electrical reading was confirmed using this test chip.
Human testers are still involved in difficult testing and quality control problems in many fields of industrial production and process control, in spite of the recent development of microelectronics and computer appli...
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Human testers are still involved in difficult testing and quality control problems in many fields of industrial production and process control, in spite of the recent development of microelectronics and computer applications. Thus far, computer-based diagnostic systems are using the von Neumann structure and are multiplexing the input signals of several sensors. An attempt is made to demonstrate that even the complicated diagnostic problems of mechanical systems can be performed with extremely short response time using: 1. parallel signal processing, and 2. problem-oriented feature extraction with fast algorithms in the time domain. The system contains general purpose, single-board computers only, based on the 68000 microprocessor. The software includes programs for data acquisition, pattern recognition, and classification, and an operating system. Two examples illustrate the effectiveness of the outlined methods.
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