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proc 2014 inter conf contemporary comp informatics (ic3i)

作者： Rasiq, S. M. Krishnakumar, S. Mahatma Gandhi Univ Reg Ctr Sch Technol & Appl Sci Kochi 682024 Kerala India

ISBN: (纸本)9781479966295

In this work, we introduce a novel method for recognizing multiple objects in an image at a very high speed. The system is based on self learning high speed parallel processing devices. The system processes video streams at speed of 1000 frames per second or more. For high speed object recognition using sequential computing from an image of a video having thousands of frames per second and each image frame consists of thousands of pixels, we need very much time for executing complicated algorithms. In the traditional way of computing and recognizing, systems are very time consuming compared to our system because the traditional systems use sequential computation for recognizing, with some complicated functions. If we use other types of parallel processors like ANN for processing each pixel or group of pixels, those systems need programming and giving data to such large number of processors are practically difficult. Here we have used a self learning parallel processor device which is made for doing some kinds of particular jobs. This parallel processing devices are easy to manipulate and can be trained simultaneously. It contains memory for storing data comparators for comparing with previously stored memory etc. Training as well as functioning are in real time even if the system process thousands of image frames per second.

关键词： Object recognition parallel processors self learning Multiple objects

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Scheduling on parallel processors with varying processing times

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COMPUTERS & OPERATIONS RESEARCH 2017年第May期81卷 90-101页

作者： Rudek, Radoslaw Wroclaw Univ Econ Inst Business Informat Komandorska 118-120 PL-53345 Wroclaw Poland

In this paper, we construct the pseudopolynomial dynamic programming algorithm that optimally solves the parallel identical processor scheduling problem to minimize the maximum job completion times (makespan) under varying processing times. They can be described by an arbitrary monotonic function dependent on the number of previously processed jobs, which can model learning or aging effects. Beside the canonical dynamic programming algorithm, we provide its efficient parallel fast version, which solves moderate problem instances of the problem within reasonable time and memory usage. Additionally, on the basis of the constructed algorithm, a fully polynomial time approximation scheme for the considered problem is provided. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： Scheduling parallel processors Learning effect Aging effect Dynamic programming FPTAS

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AN ASYNCHRONOUS DISTRIBUTED APPROACH FOR THE SIMULATION OF BEHAVIOR-LEVEL MODELS ON parallel processors

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1995年第6期6卷 639-652页

作者： GHOSH, S YU, ML AT&T BELL LABS HOLMDELNJ 07733

Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor, The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free, Additionally, it includes a new technique [6] for modeling the timing of digital systems that guarantees the accuracy of the simulation results, In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB [2] or VHDL [1]. Behavior models are popular be;cause of their flexibility;however, they execute excruciatingly slow on uniprocessor computers, The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors, In this approach, a design is first partitioned by the user and the behavior models corresponding to the digital components of each partition are assigned to a unique processor of the parallel processor system. In course of execution, a behavior model receives signal transitions from other models through the explicit communication links, termed protocols, that model the connectivity of the digital design, Every model is completely unaware of the existence of other entities in the simulation system and is solely responsible for accurately scheduling its execution on the underlying processor, Thus, scheduling is distributed in the models and the approach, like the Chandy-Misra algorithm [11], does not require any knowledge of the global simulation time, However

关键词： DISTRIBUTED SIMULATION DIGITAL SYSTEMS SIMULATION ASYNCHRONOUS ALGORITHMS parallel processors

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Scheduling preemptable tasks on parallel processors with limited availability

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parallel COMPUTING 2000年第9期26卷 1195-1211页

作者： Blazewicz, J Drozdowski, M Formanowicz, P Kubiak, W Schmidt, G Poznan Univ Technol Inst Comp Sci Poznan Poland Mem Univ Newfoundland Fac Business Adm St Johns NF Canada Univ Saarland Dept Informat & Technol Management D-6600 Saarbrucken Germany

It is well known that in the majority of cases the problem of preemptive task scheduling on m parallel identical processors with the objective of minimizing makespan can be solved in polynomial time. For example, for tree-like precedence constraints the algorithm of Muntz and Coffman can be applied. In this paper, this problem is generalized to cover the case of parallel processors which are available in certain time intervals only. It will be shown that this problem becomes NP-hard in the strong sense in case of trees and identical processors. If tasks form chains and are processed by identical processors with a staircase pattern of availability, the problem can be solved in low-order polynomial time for C-max criterion, and a linear programming approach is required for L-max criterion. Network flow and linear programming approaches will be proposed for independent tasks scheduled on, respectively, uniform and unrelated processors with arbitrary patterns of availability for schedule length and maximum lateness criteria. (C) 2000 Published by Elsevier Science B.V. All rights reserved.

关键词： preemptive scheduling parallel processors limited machine availability linear programming computational complexity

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Scheduling with deterioration effects and maintenance activities under parallel processors

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ENGINEERING OPTIMIZATION 2021年第12期53卷 2070-2087页

作者： He, Hongyu Hu, Yang Liu, Wei-Wei Dalian Commod Exchange Postdoctoral Mobile Stn Dalian Peoples R China Shenyang Aerosp Univ Sch Sci Shenyang Peoples R China Shenyang Sport Univ Dept Sci Shenyang Peoples R China

This article considers unrelated parallel processor scheduling problems with deterioration effects and processor maintenance activities. In this case, deterioration occurs during processing. A maintenance activity on a parallel processor is allowed after a job is processed, and the maintenance time is a fixed constant. After the maintenance work is completed, the processor is restored to the initial state, and job deterioration starts again. The goal of this article is to determine the location of the processor maintenance activity and to find the optimal sequence to minimize the total completion time and total machine load. It is shown in this article that these problems are polynomial-time solvable and the corresponding algorithms are provided.

关键词： Scheduling parallel processors machine maintenance deterioration effect

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MADCAPP - MEASUREMENT AND ANALYSIS OF HIGH-LEVEL COMMUNICATIONS OF ASYNCHRONOUS DISTRIBUTED ALGORITHMS ON parallel processors

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SIMULATION 1992年第2期59卷 127-133页

作者： GILLIS, CW GHOSH, S [o_1]Division of Engineering Brown University Providence Rhode Island 02912

The issue of correctness of complex asynchronous distributed algorithms implemented on loosely coupled parallel processor systemsis difficult to address given the lack of effective debugging tools. In such systems, messages propagate asynchronously over physical connections and precise knowledge of the state of every message in the system at any instant of time is difficult to obtain. For a particular class of asynchronous distributed algorithms [1,2,5] that may be characterized by independent models that execute asynchronously on the processors and interact with one another only through explicit messages, the following reasoning applies. Information on the flow and content of messages and the activity of the processors is significant towards understanding the functional correctness of the implementation. This paper proposes a new approach, MADCAPP, to measure and analyze high-level message communication and the activity level of the processors.

关键词： DEBUGGING DISTRIBUTED ALGORITHMS parallel processors VISUAL DISPLAY DISTRIBUTED DEBUGGING

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Minimizing the total weighted late work in scheduling of identical parallel processors with communication delays

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APPLIED MATHEMATICAL MODELLING 2014年第15-16期38卷 3975-3986页

作者： Abasian, Foroogh Ranjbar, Mohammad Salari, Majid Davari, Morteza Khatami, Seyed Morteza Ferdowsi Univ Mashhad Fac Engn Dept Ind Engn Mashhad Iran Katholieke Univ Leuven Fac Business & Econ Res Grp Operat Management Leuven Belgium

This paper addresses a certain type of scheduling problem that arises when a parallel computation is to be executed on a set of identical parallel processors. It is assumed that if two precedence-related tasks are processed on two different processors, due to the information transferring, there will be a task-dependent communication delay between them. For each task, a processing time, a due date and a weight is given while the goal is to minimize the total weighted late work. An integer linear mathematical programming model and a branch-and-bound algorithm have been developed for the proposed problem. Comparing the results obtained by the proposed branch-and-bound algorithm with those obtained by CPLEX, indicates the effectiveness of the method. (C) 2014 Elsevier Inc. All rights reserved.

关键词： Scheduling parallel processors Communication delay Branch-and-bound algorithm

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Dynamic on-line task scheduling on parallel processors

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PERFORMANCE EVALUATION 2001年第2-3期46卷 219-233页

作者： Xia, CH Michailidis, G Bambos, N IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA Univ Michigan Dept Stat Ann Arbor MI 48109 USA Stanford Univ Dept Elect Engn Stanford CA 94305 USA Stanford Univ Dept Management Sci & Engn Stanford CA 94305 USA

The problem of scheduling on-line a stream of multi-tasked jobs on a set of parallel processors is considered. The goal is to minimize the average sojourn time experienced by each individual job in the system. The arriving jobs are comprised of parallel applications, each consisting of multiple independent tasks that are instantaneously assigned to processor queues upon its arrival to the system. The processors independently and concurrently service the tasks in their local queues which are first-come-first-served (FCFS). A job can depart from the system only when ail its tasks have been executed and reassembled into the original single-job structure;until then, completed tasks are placed in a reassembly queue. All tasks have i.i.d. memoryless exponential service times and any task can be processed by any processor. Migration of tasks between queues after their initial allocation-is not allowed. This model captures the main features of multiprocessor computer systems executing parallel programs. The key scheduling issue is as follows. When some queue backlogs are small, an incoming job should spread its tasks to those lightly loaded queues in order to take advantage of the parallel processing gain and lower its processing delay. On the other hand, when all queues are fairly congested, the job should schedule all its tasks sequentially in a single queue to avoid excessive reassembly delay (due to backlog fluctuations) and lower its task synchronization delay. In this paper, the trade-off between these two objectives is quantified and it is shown that the optimal schedule's structure is based on backlog thresholds. Moreover, an off-line mechanism for determining these thresholds is provided, and further characteristics of the optimal scheduling policy under special cases is discussed. Finally, asymptotics and approximations for systems comprised of a large number of processors are considered. (C) 2001 Elsevier Science B.V. All rights reserved.

关键词： task schedule parallel processors backlog thresholds

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APPLICATION OF parallel GENETIC ALGORITHMS TO GENERATION EXPANSION PLANNING USING parallel processors

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ELECTRICAL ENGINEERING IN JAPAN 1995年第6期115卷 71-81页

作者： FUKUYAMA, Y UEKI, Y Fuji Electric Co. R&D Ltd

This paper presents an application of parallel genetic algorithms (PGA) to the optimal long-range generation expansion planning. The problem can be formulated as a combinatorial optimization problem that determines the order of introduced generation units at each interval of the year. The proposed method considers introduced power limits of each technology, maximum loads at each interval, and load duration curves at each interval. Appropriate string representation for the problem is presented. Binary and decimal coding and three selection methods are compared. The method is developed on a transputer that is one of the parallel processors. The feasibility of the proposed method is demonstrated using a typical expansion problem with four technologies and five intervals. The method is then compared with conventional dynamic programming and a simple genetic algorithm with promising results.

关键词： GENERATION EXPANSION PLANNING OPTIMAL GENERATION INTRODUCTION COMBINATORIAL OPTIMIZATION parallel GENETIC ALGORITHM parallel processors

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Power Quality Parameters Calculation Using FPGA Embedded parallel processors in Compliance with the IEC 61000-4-30 Standard

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JOURNAL OF CONTROL AUTOMATION AND ELECTRICAL SYSTEMS 2022年第4期33卷 1249-1260页

作者： Luiz, Max M. Duque, Tales F. Almeida, Afonso H. S. Kapisch, Eder B. Silva, Leandro R. M. Lima, Marcelo A. A. Univ Fed Juiz de Fora Juiz De Fora MG Brazil

This work presents the implementation of a power quality (PQ) parameters calculation system based on the use of parallel processors embedded in field-programmable gate array (FPGA). The novelty in the proposal is that the processors used in the FPGA implementation were developed to be automatically customizable, providing hardware resource optimization. The algorithms implemented in each processor follow the guidelines described in the IEC 61000-4-30 standard, for class A equipment. In order to show the effective operation of the implementation, the system was subjected to a functional simulation, using the ModelSim (R) software, from the manufacturer Intel (R). A functional prototype was also developed using a Cyclone (R) V FPGA evaluation board, to perform practical tests. The experimental results show that the system is able to calculate all parameters according to the requirements specified by the IEC 61000-4-30 standard for class A devices using minimum hardware resources, such as logic elements, memory and DSP blocks. For further analysis, the calculated parameters are then stored in a database based on PostgreSQL (R) platform. In order to enable visualizing and analyzing these results, an interactive visualization panel was developed using the Grafana (R) platform.

关键词： Power quality parameters parallel processors Hardware optimization FPGA IEC 61000-4-30

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