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Lower bounds for online scheduling on four processors

JOURNAL OF SCHEDULING 2025年 1-16页

作者： Braun, O. Chung, F. Graham, R. L. Univ Calif San Diego La Jolla CA 92093 USA

We explore lower bounds concerning the makespan of any online scheduling algorithm for the parallel processor scheduling problem with four processors. We prove that any online algorithm exhibits a makespan of at least root 3 times that of an optimal offline schedule, minus an additional constant of 2 - root 3, thus yielding an asymptotic competitive ratio of root 3. Moreover, specific absolute competitive ratios 3 - & varepsilon;(r), where & varepsilon;(r )> 0 depends on the number of tasks that have to be scheduled, are established for scenarios involving a finite number of tasks.

关键词： Online scheduling parallel processors Makespan Competitive analysis Lower bounds

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Rei: A Reconfigurable Interconnection Unit for Array-Based CNN Accelerators

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2023年第4期11卷 895-906页

作者： Darbani, Paria Beitollahi, Hakem Lotfi-Kamran, Pejman Iran Univ Sci & Technol Sch Comp Engn Tehran *** Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran *** Iran

Convolutional Neural Network (CNN) is used in many real-world applications due to its high accuracy. The rapid growth of modern applications based on learning algorithms has increased the importance of efficient implementation of CNNs. The array-type architecture is a well-known platform for the efficient implementation of CNN models, which takes advantage of parallel computation and data reuse. However, accelerators suffer from restricted hardware resources, whereas CNNs involve considerable communication and computation load. Furthermore, since accelerators execute CNN layer by layer, different shapes and sizes of layers lead to suboptimal resource utilization. This problem prevents the accelerator from reaching maximum performance. The increasing scale and complexity of deep learning applications exacerbate this problem. Therefore, the performance of CNN models depends on the hardware's ability to adapt to different shapes of different layers to increase resource utilization. This work proposes a reconfigurable accelerator that can efficiently execute a wide range of CNNs. The proposed flexible and low-cost reconfigurable interconnect units allow the array to perform CNN faster than fixed-size implementations (by 45.9% for ResNet-18 compared to the baseline). The proposed architecture also reduces the on-chip memory access rate by 36.5% without compromising accuracy.

关键词： Adaptable architectures array and vector processors image processing and computer vision parallel processors reconfigurable hardware special-purpose and application-based systems

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Solving a new bi-objective mathematical model for a hybrid flow shop scheduling problem with robots and fuzzy maintenance time

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COMPUTERS & INDUSTRIAL ENGINEERING 2023年第1期182卷

作者： Ghodratnama, Ali Amiri-Aref, Mehdi Tavakkoli-Moghaddam, Reza Kharazmi Univ Fac Engn Dept Ind Engn Tehran Iran Kedge Business Sch Dept Operat Management & Informat Syst Paris France Univ Tehran Coll Engn Sch Ind Engn Tehran Iran

This paper presents a bi-objective mathematical model of a hybrid flow shop scheduling problem (HFSSP) with robots and fuzzy maintenance time. The proposed model minimizes the mean completion time of jobs and the total cost of the processes based on maintenance costs and incurred transportation costs via robots. A fuzzy chance-constrained programming (FCCP) model is used to present its deterministic-equivalent problem. It is then solved by two multi-objective decision-making approaches, namely LP-metric and goal attainment (GA). A sensitivity analysis of the weights of the objective functions is conducted and the behavior of the model is studied for each instance. Also, a TOPSIS (the technique for order of preference by similarity to ideal solution) method is used to rank the efficiency of the proposed solution approaches. Future research areas are also suggested.

关键词： Hybrid flow shop scheduling parallel processors Maintenance Robots Goal attainment Fuzzy uncertainty

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Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator 33

Co-design of a novel CMOS highly parallel, low-power, multi-...

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33rd Microelectronics Design & Test Symposium (MDTS)

作者： Hokenmaier, W. Jurasek, R. Bowen, E. Granger, R. Odom, D. Green Mt Semicond Inc Semicond Hardware Dev Burlington VT 05401 USA Non Von LLC Software Algorithm & Architecture Design Lyme NH USA

ISBN: (纸本)9798350364651;9798350364668

Why do security cameras, sensors, and siri use cloud servers instead of on-board computation? The lack of very-lowpower, high-performance chips greatly limits the ability to field untethered edge devices. We present the NV-1, a new low-power ASIC AI processor that greatly accelerates parallel processing (similar to 10X) with dramatic reduction in energy consumption (> 100X), via many parallel combined processor-memory units, i.e., a drastically non-von-Neumann architecture, allowing very large numbers of independent processing streams without bottlenecks due to typical monolithic memory. The current initial prototype fab arises from a successful co-development effort between algorithm- and software-driven architectural design and VLSI design realities. An innovative communication protocol minimizes power usage, and data transport costs among nodes were vastly reduced by eliminating the address bus, through local target address matching. Throughout the development process, the software/architecture team was able to innovate alongside the circuit design team's implementation effort. A digital twin of the proposed hardware was developed early on to ensure that the technical implementation met the architectural specifications, and indeed the predicted performance metrics have now been thoroughly verified in real hardware test data. The resulting device is currently being used in a fielded edge sensor application;additional proofs of principle are in progress demonstrating the proof on the ground of this new real-world extremely low-power high-performance ASIC device.

关键词： co-design low-power design parallel processors neural network accelerator memory instruction set design

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HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2022年第12期33卷 4368-4382页

作者： Kurth, Andreas Forsberg, Bjoern Benini, Luca Integrated Syst Lab CH-8092 Zurich Switzerland Swiss Fed Inst Technol D ITET Dept Informat Technol & Elektrotech CH-8092 Zurich Switzerland Univ Bologna DEIS I-40126 Bologna BO Italy

Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and high performance. To realize the full potential of heterogeneous computers, however, many hardware and software design challenges have to be overcome. While architectural and system simulators can be used to analyze heterogeneous computers, they are faced with unavoidable compromises between simulation speed and performance modeling accuracy. In this work we present HEROv2, an FPGA-based research platform that enables accurate and fast exploration of heterogeneous computers consisting of accelerators based on clusters of 32-bit RISC-V cores and an application-class 64-bit ARMv8 or RV64 host processor. HEROv2 allows to seamlessly share data between 64-bit host s and 32-bit accelerators and comes with a fully open-source on-chip network, a unified heterogeneous programming interface, and a mixed-data-model, mixed-ISA heterogeneous compiler based on LLVM. We evaluate HEROv2 in four case studies from the application level over toolchain and system architecture down to accelerator microarchitecture. We demonstrate how HEROv2 enables effective research and development on the full stack of heterogeneous computing. For instance, the compiler can tile loops and infer data transfers to and from the accelerators, which leads to a speedup of up to 4.4 x compared to the original program and in most cases is only 15% slower than a handwritten implementation, which requires 2.6 x more code.

关键词： Hardware Program processors Codes Computers System-on-chip Programming Engines Heterogeneous (Hybrid) systems parallel processors shared memory hardware software interfaces system architectures

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Computational Analysis of parallel Techniques for Nonlinear Biomedical Engineering Problems

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ALGORITHMS 2024年第12期17卷 575-575页

作者： Shams, Mudassir Carpentieri, Bruno Free Univ Bozen Bolzano BZ Fac Engn I-39100 Bolzano Italy Balikesir Univ Dept Math TR-10145 Balikesir Turkiye Riphah Int Univ I 14 Dept Math & Stat Islamabad 44000 Pakistan

In this study, we develop new efficient parallel techniques for solving both distinct and multiple roots of nonlinear problems at the same time. The parallel techniques represent an innovative contribution to the discipline, with local convergence of the ninth order. Theoretical research shows the rapid convergence and effectiveness of the proposed parallel schemes. To assess the suggested scheme's stability and consistency, we look at certain biomedical engineering applications, such as osteoporosis in Chinese women, blood rheology, and differential equations. Overall, detailed analyses of convergence behavior, memory utilization, computational time, and percentage computational efficiency show that the novel parallel techniques outperform the traditional methods. The proposed methods would be more suitable for large-scale computational problems in biomedical applications due to their advantages in memory efficiency, CPU time, and error reduction.

关键词： memory utilization computational time parallel processors error graph

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PITON: A MANYCORE PROCESSOR FOR MULTITENANT CLOUDS

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IEEE MICRO 2017年第2期37卷 70-80页

作者： McKeown, Michael Fu, Yaosheng Tri Nguyen Zhou, Yanqi Balkind, Jonathan Lavrov, Alexey Shahrad, Mohammad Payne, Samuel Wentzlaff, David Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Princeton NJ 08544 USA

PITON IS A 25-CORE MANYCORE PROCESSOR THAT REIMAGINES THE DATACENTER ARCHITECTURE, BREAKING DOWN BARRIERS BETWEEN CHIPS, NODES, AND RACKS, AND ENABLING FLEXIBILITY, PERFORMANCE, AND ENERGY EFFICIENCY AT SCALE. IT IS DESIGNED NOT ONLY AS A SINGLE CHIP, BUT AS A LARGE-SCALE SYSTEM. PITON SUPPORTS SHARED MEMORY ACROSS ARBITRARY CORES IN THE SYSTEM AND IS TAILORED TO INFRASTRUCTURE-AS-A-SERVICE CLOUDS.

关键词： Bandwidth cloud computing Computer architecture Data centers Energy efficiency Large-scale systems low-power design microprocessors MIMD processors multicore/single-chip multiprocessors Multiprocessing systems multiprocessor systems multithreaded processors on-chip interconnection networks parallel processors processor architectures servers

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Worklist-Directed Prefetching

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2017年第2期16卷 170-173页

作者： Zhang, Dan Ma, Xiaoyu Chiou, Derek Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

Researchers have demonstrated the benefits of hardware worklist accelerators, which offload scheduling and load balancing operations in parallel graph applications. However, many of these applications are still heavily memory latency-bound due to the irregular nature of graph data structure access patterns. We utilize the fact that the accelerator has knowledge of upcoming work items to accurately issue prefetch requests, a technique we call worklist-directed prefetching. A credit-based system to improve prefetch timeliness and prevent cache thrashing is proposed. The proposed prefetching scheme is simulated on a 64-core CMP with a hardware worklist accelerator on several graph algorithms and inputs. Enabling worklist-directed prefetching into the L2 cache results in an average speedup of 1.99, and up to 2.35 on Breadth-First Search.

关键词： Prefetching graph problems parallel processors accelerators

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SAT-Based Compilation to a non-vonNeumann Processor 17

SAT-Based Compilation to a non-vonNeumann Processor

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IEEE/ACM 36th International Conference on Computer-Aided Design (ICCAD)

作者： Chaudhuri, Samit Hetzel, Asmus Wave Comp Campbell CA 95008 USA Amazon Dev Ctr Berlin Germany

ISBN: (纸本)9781538630938

This paper describes a compilation technique used to accelerate dataflow computations, common in deep neural network computing, onto Coarse Grained Reconfigurable Array (CGRA) architectures. This technique has been demonstrated to automatically compile dataflow programs onto a commercial massively parallel CGRA-based dataflow processor (DPU) containing 16000 processing elements. The DPU architecture overcomes the von Neumann bottleneck by spatially flowing and reusing data from local memories, and provides higher computation efficiency compared to temporal parallel architectures such as GPUs and multi-core CPUs. However, existing software development tools for CGRAs are limited to compiling domain specific programs to processing elements with uniform structures, and are not effective on complex micro architectures where latencies of memory access vary in a nontrivial fashion depending on data locality. A primary contribution of this paper is to provide a general algorithm that can compile general dataflow graphs, and can efficiently utilize processing elements with rich micro-architectural features such as complex instructions, multi-precision data paths, local memories, register files, switches etc. Another contribution is a uniquely innovative application of Boolean Satisfiability to formally solve this complex, and irregular optimization problem and produce high-quality results comparable to hand-written assembly code produced by human experts. A third contribution is an adaptive windowing algorithm that harnesses the complexity of the SAT-based approach and delivers a scalable and robust solution.

关键词： dataflow CGRA neural networks parallel processors compilers satisfiability scheduling routing

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Evaluation and Mitigation of Radiation-Induced Soft Errors in Graphics Processing Units

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IEEE TRANSACTIONS ON COMPUTERS 2016年第3期65卷 791-804页

作者： Goncalves de Oliveira, Daniel Alfonso Pilla, Laercio Lima Santini, Thiago Rech, Paolo Fed Univ Rio Grande Sul UFRGS Inst Informat Av Bento Goncalves9500 Campus Vale Bloco 4 Porto Alegre RS Brazil Univ Fed Santa Catarina Dept Informat & Stat Campus Univ Reitor Joao David Ferreira Lima Florianopolis SC Brazil

Graphics processing units (GPUs) are increasingly attractive for both safety-critical and High-Performance Computing applications. GPU reliability is a primary concern for both the automotive and aerospace markets and is becoming an issue also for supercomputers. In fact, the high number of devices in large data centers makes the probability of having at least a device corrupted to be very high. In this paper, we aim at giving novel insights on GPU reliability by evaluating the neutron sensitivity of modern GPUs memory structures, highlighting pattern dependence and multiple errors occurrences. Additionally, a wide set of parallel codes are exposed to controlled neutron beams to measure GPUs operative error rates. From experimental data and algorithm analysis we derive general insights on parallel algorithms and programming approaches reliability. Finally, error-correcting code, algorithm-based fault tolerance, and duplication with comparison hardening strategies are presented and evaluated on GPUs through radiation experiments. We present and compare both the reliability improvement and imposed overhead of the selected hardening solutions.

关键词： GPU fault-tolerance neutron sensitivity parallel processors reliability

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