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检索条件"主题词=parallel programming models"

共 93 条记录，以下是71-80 订阅

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The AMPERE Project: A Model-driven development framework for highly parallel and EneRgy-Efficient computation supporting multi-criteria optimization 23

The AMPERE Project: A Model-driven development framework for...

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IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)

作者： Quinones, Eduardo Royuela, Sara Scordino, Claudio Gai, Paolo Pinho, Luis Miguel Nogueira, Luis Rollo, Jan Cucinotta, Tommaso Biondi, Alessandro Hamann, Arne Ziegenbein, Dirk Saoud, Hadi Soulat, Romain Forsberg, Bjoern Benini, Luca Mando, Gianluca Rucher, Luigi Barcelona Supercomp Ctr Barcelona Spain Evidence Srl Pisa Italy Inst Super Engn Porto Porto Portugal Sysgo Prague Czech Republic Scuola Super Sant Anna Pisa Italy Bosch Stuttgart Germany Thales Res & Technol Palaiseau France Swiss Fed Inst Technol Zurich Switzerland Thales Italy Florence Italy

ISBN: (纸本)9781728169583

The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms. The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system.

关键词： parallel programming models parallel and heterogeneous embedded processor architectures model-driven approaches safety-critical embedded systems

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Overlapping Communication and Computation with ExaMPI's Strong Progress and Modern C plus plus Design

Overlapping Communication and Computation with ExaMPI's Stro...

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8th Workshop on Exascale MPI (ExaMPI)

作者： Schafer, Derek Hines, Thomas Suggs, Evan Drake Rufenacht, Martin Skjellum, Anthony Univ Tennessee Chattanooga TN 37403 USA Leibniz Supercomp Ctr Bavaria Germany

ISBN: (纸本)9781665411080

ExaMPI is a modern, C++17+ MPI implementation designed for modularity, extensibility, and understandability. In this work, we overview functionality new to ExaMPI since its initial release, including Libfabric-based network transport support. We also explain our rationale for why and how we choose to add new MPI features (and defer others). Lastly, we measured the latency of the aforementioned transports in ExaMPI and found that ExaMPI, while having slightly higher latency than other production MPIs, is competitive. It is no longer uncommon to see MPI applications using extra MPI calls during non-blocking MPI operations to coax MPI's progress engine. Strong, asynchronous progress (aka application bypass) in MPI is instead based on the premise that an application asks MPI to perform a non-blocking communication in the background and MPI completes said communication without requiring any additional MPI calls from the application to advance the underlying transport. Strong progress often requires an additional background thread, but with the current trend in exascale computing, cores appear to be in excess. Indeed, for earlier MPI implementations that supported it well, strong progress enabled overlap and reduced time to completion for some MPI applications. However, enabling or adding strong progress to existing MPI implementations is not straightforward;changing such implementations is cumbersome, difficult, invasive, and time-consuming-a key motivation for our research MPI implementation, ExaMPI. Specifically, we tested the ability for ExaMPI's strong progress engine to enable overlap communication and computation, finding that considerable overlap is achieved without needing additional MPI "helper" calls such as MPI_Test.

关键词： MPI middleware architecture parallel programming models overlap performance portability

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Enabling Cloud Interoperability with COMPSs

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18th International Conference on Euro-Par parallel Processing

作者： Marozzo, Fabrizio Lordan, Francesc Rafanell, Roger Lezzi, Daniele Talia, Domenico Badia, Rosa M. Univ Calabria DEIS I-87036 Arcavacata Di Rende CS Italy Spanish Council Sci Res CSIC Artificial Intelligence Res Inst IIIA Madrid Spain Univ Calabria DEIS Arcavacata Di Rende Italy CNR ICAR Arcavacata Di Rende Italy

ISBN: (纸本)9783642328206

The advent of Cloud computing has given to researchers the ability to access resources that satisfy their growing needs, which could not be satisfied by traditional computing resources such as PCs and locally managed clusters. On the other side, such ability, has opened new challenges for the execution of their computational work and the managing of massive amounts of data into resources provided by different private and public infrastructures. COMP Superscalar (COMPSs) is a programming framework that provides a programming model and a runtime that ease the development of applications for distributed environments and their execution on a wide range of computational infrastructures. COMPSs has been recently extended in order to be interoperable with several cloud technologies like Amazon, OpenNebula, Emotive and other OCCI compliant offerings. This paper presents the extensions of this interoperability layer to support the execution of COMPSs applications into the Windows Azure Platform. The framework has been evaluated through the porting of a data mining workflow to COMPSs and the execution on an hybrid testbed.

关键词： parallel programming models Cloud computing Data mining PaaS

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Online Scalability Characterization of Data-parallel Programs on Many Cores 16

Online Scalability Characterization of Data-Parallel Program...

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International Conference on parallel Architectures and Compilation (PACT)

作者： Cho, Younghyun Oh, Surim Egger, Bernhard Seoul Natl Univ Dept Comp Sci & Engn Seoul South Korea

ISBN: (纸本)9781450341219

We present an accurate online scalability prediction model for data-parallel programs on NUMA many-core systems. Memory contention is considered to be the major limiting factor of program scalability as data parallelism limits the amount of synchronization or data dependencies between parallel work units. Reflecting the architecture of NUMA systems, contention is modeled at the last-level caches of the compute nodes and the memory nodes using a two level queuing model to estimate the mean service time of the individual memory nodes. Scalability predictions for individual or co-located parallel applications are based solely on data obtained during a short sampling period at runtime;this allows the presented model to be employed in a variety of scenarios. The proposed model has been implemented into an open-source OpenCL and the GNU OpenMP runtime and evaluated on a 64-core AMD system. For a wide variety of parallel workloads and configurations, the evaluations show that the model is able to predict the scalability of data-parallel kernels with high accuracy.

关键词： performance prediction queuing models multi-socket multi-core architectures openmp many-core resource management performance modeling opencl space-shared scheduling memory contention last-level caches parallel programming models performance scalability data-parallelism numa architectures memory architectures

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A Runtime Implementation of OpenMP Tasks

A Runtime Implementation of OpenMP Tasks

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7th International Workshop on OpenMP (IWOMP)

作者： LaGrone, James Aribuki, Ayodunni Addison, Cody Chapman, Barbara Univ Houston Houston TX 77004 USA Texas Instruments Inc Stafford TX 77477 USA

ISBN: (纸本)9783642214875

Many task-based programming models have been developed and refined in recent years to support application development for shared memory platforms. Asynchronous tasks are a powerful programming abstraction that offer flexibility in conjunction with great expressivity. Research involving standardized tasking models like OpenMP and non-standardized models like Cilk facilitate improvements in many tasking implementations. While the asynchronous task is arguably a fundamental element of parallel programming, it is the implementation, not the concept, that makes all the difference with respect to the performance that is obtained by a program that is parallelized using tasks. There are many approaches to implementing tasking constructs, but few have also given attention to providing the user with some capabilities for fine tuning the execution of their code. This paper provides an overview of one OpenMP implementation, highlights its main features, discusses the implementation, and demonstrates its performance with user controlled runtime variables.

关键词： OpenMP Tasks parallel programming models Runtime Systems

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Managing Heterogeneous Resources in HPC Systems 18

Managing Heterogeneous Resources in HPC Systems

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9th Workshop on parallel programming and Run-Time Management Techniques for Many-Core Architectures (PARMA) / 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (DITAM)

作者： Agosta, Giovanni Fornaciari, William Massari, Giuseppe Pupykina, Anna Reghenzani, Federico Zanella, Michele Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781450364447

To sustain performance while facing always tighter power and energy envelopes, High Performance Computing (HPC) is increasingly leveraging heterogeneous architectures. This poses new challenges: to efficiently exploit the available resources, both in terms of hardware and energy, resource management must support a wide range of different heterogeneous devices and programming models that target different application domains. We present a strategy for resource management and programming model support for heterogeneous accelerators for HPC systems with requirements targeting performance, power and predictability. We show how resource management can, in addition to allowing multiple applications to share a set of resources, reduce the burden on the application developer and improve the efficiency of resource allocation.

关键词： parallel programming models Resource Management Heterogeneous Architectures High Performance Computing

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Enabling Multi-threading in Heterogeneous Quantum-Classical programming models

Enabling Multi-threading in Heterogeneous Quantum-Classical ...

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37th IEEE International parallel and Distributed Processing Symposium (IPDPS)

作者： Hayashi, Akihiro Adams, Austin Young, Jeffrey McCaskey, Alexander Dumitrescu, Eugene Sarkar, Vivek Conte, Thomas M. Georgia Inst Technol Atlanta GA 30332 USA NVIDIA Corp Santa Clara CA USA Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9798350311990

While quantum computers enable significant performance improvements for certain classes of applications, building a well-defined programming model has been a pressing issue. In this paper, we address some of the key limitations to realizing a generic heterogeneous parallel programming model for quantumclassical heterogeneous platforms. We discuss our experience in enabling user-level multi-threading in QCOR [1] as well as challenges that need to be addressed for programming future quantum-classical systems. Specifically, we discuss our design and implementation of introducing C++-based parallel constructs to enable 1) parallel execution of a quantum kernel with std::thread and 2) asynchronous execution with std::async. To do so, we provide a detailed overview of the current implementation of the QCOR programming model and runtime, and discuss how we add 1) thread-safety to some of its user-facing API routines, and 2) increase parallelism in QCOR by removing data races that inhibit multi-threading so as to better utilize available computing resources. We also present preliminary performance results with the Quantum++ [2] back end on a single-node Ryzen9 3900X machine that has 12 physical cores (24 hardware threads) with 128GB of RAM. The results show that running two Bell kernels with 12 threads per kernel in parallel outperforms running the kernels one after the other each with 24 threads (1.63x improvement). In addition, we observe the same trend when running two Shor's algorthm kernels in parallel (1.22x faster than executing the kernels one after the other). Furthermore, the parallel version is better in terms of strong scalability. We believe that our design, implementation, and results will open up an opportunity not only for 1) enabling quicker prototyping of parallel-aware quantum-classical algorithms on quantum circuit simulators in the short-term, but also for 2) realizing a generic parallel programming model for quantumclassical heterogeneous platforms in

关键词： Quantum-Classical programming models parallel programming models QCOR Heterogeneous Computing

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Demistifying HPC-Quantum integration: it's all about scheduling

Demistifying HPC-Quantum integration: it's all about schedul...

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Workshop on High Performance and Quantum Computing Integration (HPQCI)

作者： Viviani, Paolo LINKS Fdn Turin Italy

ISBN: (纸本)9798400706431

Recent research on the integration between HPC and quantum computer was mostly focused on the software stack and quantum circuit compilation aspects, neglecting critical issues like HPC resource allocation and job scheduling given the scarcity of QPUs, and disregarding the heterogeneity of current quantum technologies and their computational models (e.g., digital vs. analogue). This work would like to bring the attention to issues that are critical to achieve integration with operational HPC environments given the current status of quantum computers maturity and heterogeneity.

关键词： quantum computing HPC parallel programming models job scheduling resource allocation

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Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management 31

Improving Performance of HPC Kernels on FPGAs Using High-Lev...

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31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Filgueras, Antonio Vidal, Miquel Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Univ Politecn Cataluna Barcelona Spain Barcelona Supercomp Ctr Barcelona Spain

In state-of-the-art FPGA, especially in chiplet-based devices, place and route has become an important challenge due to an increase in device size and complexity. In the same way, off-chip memory resources have grown ... 详细信息

ISBN: (纸本)9798350312058

关键词： FPGA FPGA design tools high performance computing high-level synthesis matrix multiplication parallel programming models

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A unified methodology for a fast benchmarking of parallel architecture

A unified methodology for a fast benchmarking of parallel ar...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Guerre, Alexandre Acquaviva, Jean-Thomas Lhuillier, Yves CEA LIST Embedded Comp Lab F-91191 Gif Sur Yvette France

ISBN: (纸本)9783981537024

Benchmarking of architectures is today jeopardized by the explosion of parallel architectures and the dispersion of parallel programming models. parallel programming requires architecture dependent compilers and languages as well as high programming expertise. Thus, an objective comparison has become a harder task. This paper presents a novel methodology to evaluate and to compare parallel architectures in order to ease the programmer work. It is based on the usage of microbenchmarks, code profiling and characterization tools. The main contribution of this methodology is a semi-automatic prediction of the performance for sequential applications on a set of parallel architectures. In addition the performance estimation is correlated with the cost of other criteria such as power or portability. Our methodology prediction was validated on an industrial application. Results are within a range of 20%.

关键词： benchmark testing parallel architectures parallel programming performance evaluation software tools architecture dependent compilers characterization tools code profiling microbenchmarks parallel architecture benchmarking parallel programming models performance estimation portability programming languages semiautomatic performance prediction sequential applications Benchmark testing Computational modeling Databases Kernel parallel architectures programming

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