As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Amon...
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As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallelturbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallelturbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps.
As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future broadcasting systems. High throughput and l...
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ISBN:
(纸本)9781509049370
As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future broadcasting systems. High throughput and low latency are two basic requirements that the future systems need to meet. parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallelturbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. The latency of parallelturbo decoder after implementation can be as less as 23.2us at a clock rate of 250 MHz and the throughput can reach up to 6.92Gbps.
This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Tu...
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This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. turbo codes being widely used for error correction in today's consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm(2) area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.
HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have recently been proposed t...
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ISBN:
(纸本)9780769537825
HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithm used in WCDMA based systems does not freely allows to use them due to high percentage of memory conflicts. This paper provides a comprehensive analysis for reduction of interleaver memory conflicts while generating more than one address in a single clock cycle. It also provides trade-off analysis in terms of area and power efficiency for multiple architectures for different functions involved in the interleaver design. The final architecture supports processing of two parallel SISO blocks and manages the conflicts by applying different approaches like stream misalignment, memory division and small FIFO buffer. The proposed architecture is low cost and consumes 4.3K gates at a frequency of 150 MHz. This work also focuses on reduction of preprocessing overheads by introducing the segment based modulo computation, thus providing flirt her relaxation to SISO decoding process.
An FPGA implementation of a highly parallel and configurable architecture for turbodecoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for soft...
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ISBN:
(纸本)9781479920785
An FPGA implementation of a highly parallel and configurable architecture for turbodecoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initialization method and the parallel and sliding window techniques is used in the MAP algorithm. This allows high throughput and reduced storage requirements, as compared to other solutions. Synthesis results on Altera FPGAs show that this architecture can reach 337.6 Mbps at 8 decoding iterations.
This paper presents a low-complexity interleaver design that facilitates the high throughput turbodecoding required for next generation wireless systems. Specifically, it addresses the interleaver design issues that ...
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This paper presents a low-complexity interleaver design that facilitates the high throughput turbodecoding required for next generation wireless systems. Specifically, it addresses the interleaver design issues that arise when several Log-MAP processors are used in parallel to improve turbodecoding throughput. In such a parallel decoder, memory access contentions occur when more than one extrinsic value is to be written to or read from the same memory block at the same time. These contentions may be avoided by designing contention-free (CF) interleavers that incorporate hardware constraints into the interleaver description. The paper first derives bounds on the number of CF interleavers, demonstrating that the fraction of interleavers of a given size that are contention-free is quite small. In spite of this, a class of contention-free "inter-window shuffle" (IWS) interleavers are shown via simulation to achieve near-WCDMA performance. Further, the paper shows that the memory requirement of CF IWS interleavers is small compared to an alternate contention-resolving method that uses a modified memory addressing scheme. Finally, we note that the advantages of contention-free interleavers have led to the adoption of a CF quadratic permutation polynomial (QPP) interleaver in the 3GPP long term evolution (LTE) standard.
In this paper we discuss a novel storage scheme for simultaneous memory access in parallelturbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural o...
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In this paper we discuss a novel storage scheme for simultaneous memory access in parallelturbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.
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